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Comments?E-mail your comments about Synopsys documentation to [email protected] VCS®/VCSi™User GuideVersion Y-2006.06-SP2March 2008

viiiGenerating Source Files From VCD Files . . . . . . . . . . . . . . . 7-17Writing the Configuration File. . . . . . . . . . . . . . . . . . . . . .

2-32Modeling Your Design2. A nested begin block executes only if the current scope is either top.c1 or top.c3.3. VCS displays whether $activeinst poin

24-34SystemVerilog Testbench Constructs$display("s1 after pop contains %s ",s1);$write("the elements of strque are ");for (int i =

24-35SystemVerilog Testbench Constructsmodule test;bit [11:10][9:8][7:0] bit_array1;initialbeginforeach (bit_array1[dim1,dim2]) bit_array1 [dim1][d

24-36SystemVerilog Testbench ConstructsendmoduleThe $display system task displays the following:string element number 0 contains "simulation"

24-37SystemVerilog Testbench Constructsassoc_array1[7]=3'b111;foreach (assoc_array1[dim1]) $display("assoc_array1 [%1d]=%0d",

24-38SystemVerilog Testbench ConstructsList of Aggregate MethodsThe following code is an example of the aggregate method, sum() in an inline constrain

24-39SystemVerilog Testbench Constructs if(i) $display("Randomization Success"); else$display("Randomization Fails");endendp

24-40SystemVerilog Testbench ConstructsClassesThe user-defined data type, class, is composed of data members of valid SystemVerilog data types (known

24-41SystemVerilog Testbench Constructs logic [7:0] log1; } struct1;struct1 mystruct;typedef struct packed { int intt1

24-42SystemVerilog Testbench Constructssend = a * 2;endfunctiontask show();$display("q = %0d", q);endtaskendclass initial beginB b1; //de

24-43SystemVerilog Testbench Constructshandle_name = new([arguments]);Arguments are optional.Below is an example of a user-defined constructor: progra

2-33Modeling Your DesignAvoiding Circular DependencyThe $random system function has an optional seed argument. You can use this argument to make the r

24-44SystemVerilog Testbench ConstructsThe output of this program is:The value of q is 4.If a property is not initialized by the constructor, it is im

24-45SystemVerilog Testbench ConstructsNow consider the following, assuming p1 and p2 have been declared and p1 has been instantiated:p2 = new p1;The

24-46SystemVerilog Testbench Constructsinitial begin Parcel pk1 = new; Parcel pk2 = new; Parcel pk3 = new; $display("%d Parcel",

24-47SystemVerilog Testbench Constructsclass Xvdata_Class;const int pi = 31412;//const variableendclass Xvdata_Class data; initial begin

24-48SystemVerilog Testbench Constructsrand A a1;rand E e1;extern function f1();constraint c;endclass//out of class body method declared with the help

24-49SystemVerilog Testbench Constructs endendprogramThe Output of this program isAccessing enum label in constraint block through :: operator

24-50SystemVerilog Testbench ConstructsendclassNow, all of the methods and properties of Packet are part of LinkedPacket - as if they were defined in

24-51SystemVerilog Testbench Constructsendfunctionendclassclass EtherPacket extends BasePacket;function integer send(bit[31:0] data) // body of the fu

24-52SystemVerilog Testbench ConstructsMethods of non-abstract classes can also be declared virtual. In this case, the method must have a body, since

24-53SystemVerilog Testbench Constructsclass MyPacket extends Packet;task display();$display("This is the display within MyPacket");endtaske

2-34Modeling Your DesignFor example:assign out = $random(); initialbeginassign dr1 = $random();force dr2 = $random();dr3 = $random(in);These statement

24-54SystemVerilog Testbench ConstructsThis is the display within MyPacketThis is the display within YourPacketThis is a typical, albeit small, exampl

24-55SystemVerilog Testbench Constructssuper keywordThe super keyword is used from within a derived class to refer to properties of the parent class.

24-56SystemVerilog Testbench ConstructsBase: p=2Extended: q=3In the above example, the method, display() defined in Extended calls display(), which is

24-57SystemVerilog Testbench Constructsinteger q;virtual task display();super.display(); $write("Extended: q=%0d\n", q);endtaskendclassBase

24-58SystemVerilog Testbench ConstructsShows new value of the base property, p, and value of the extended property, qBase: p=2Extended: q=3The base ha

24-59SystemVerilog Testbench Constructsclass ClassA;...endclassclass Class_a extends ClassA;...endclassclass class_ab extends Class_a;...endclassclass

24-60SystemVerilog Testbench ConstructsFigure 24-1 Base and Sub ClassesWhen a subclass is instantiated, the constructor of the extended super class is

24-61SystemVerilog Testbench ConstructsFigure 24-2 Chaining Constructorswhen Class_ab is instantiated, the “new” constructor for Class_a is called. In

24-62SystemVerilog Testbench ConstructsThis will pass 5 to the new() routine associated with “Packet”.A more general approach is to use the super keyw

24-63SystemVerilog Testbench ConstructsAccessing Properties A property of an object can be accessed using the dot operator (.). The handle name for th

2-35Modeling Your DesignDealing With Unassigned NetsConsider the following example:module test(A); input A; wire A; DUT DUT_1 (A); // assign A = 1&apo

24-64SystemVerilog Testbench ConstructsOutput of programq = 3value returned by b1.send() = 8“this” keywordThe this keyword is used to unambiguously re

24-65SystemVerilog Testbench ConstructsThe following is another, complete, example. program P;class Demo;integer x=4;function integer send(integer x);

24-66SystemVerilog Testbench ConstructsClass Packet Exampleclass Packet;bit [3:0] command; //property declarationsbit [40:0] address;bit [4:0] master

24-67SystemVerilog Testbench Constructsclass myclass;...typedef struct { int int1; logic [7:0] log1; } struct1;struct1 mystruct1;...en

24-68SystemVerilog Testbench ConstructsRandom ConstraintsSystemVerilog has constructs for the random testing of a design and a means of constraining t

24-69SystemVerilog Testbench ConstructsVariable randc1 has two bits so its possible values range from 3 to 0. VCS derives a random order, or permutati

24-70SystemVerilog Testbench Constructsclass myclass; rand logic [1:0] log1,log2,log3; randc logic [1:0] log4; constraint c1 {log1 > 0;}

24-71SystemVerilog Testbench Constructslog1 = 1 log2=2 log3=0 log4=0log1 = 2 log2=0 log3=1 log4=1log1 = 1 log2=1 log3=1 log4=3log1 = 3 log2=2 log3=1 l

24-72SystemVerilog Testbench ConstructsExternal DeclarationYou can declare a constraint block outside of a class declaration.program prog1;class cl1;

24-73SystemVerilog Testbench ConstructsSet MembershipYou can use the inside operator to specify a set of possible values that VCS randomly applies to

2-36Modeling Your DesignThe designer actually meant for a code of Z to be returned, input tristated. To achieve this code, the input A needs to be ass

24-74SystemVerilog Testbench ConstructsAll these values are equally probable.In the following example, the inside operator is used to specify possible

24-75SystemVerilog Testbench ConstructsWeighted DistributionYou can use the dist operator to specify a set of values or ranges of values, where you gi

24-76SystemVerilog Testbench Constructs• A range of 1 to 2, each value in this range has a weight of 1. The := operator, when applied to a range, spec

24-77SystemVerilog Testbench Constructs constraint c1 { (norandvar == 1) -> (randcvar == 0);}endclassBus bus = new;initialbegin bus.norandvar

24-78SystemVerilog Testbench Constructsrandcvar = 0 norandvar = 0 at 13randcvar = 1 norandvar = 0 at 14When variable norandvar is 0, random-cyclic var

24-79SystemVerilog Testbench Constructs $display("randcvar = %0d norandvar = %0b at %0t", bus.randcvar, bus.norandvar,$time);endprogra

24-80SystemVerilog Testbench Constructsprogram prog;class myclass; rand bit [7:0] randvar;endclassclass myextclass extends myclass; rand myclass lef

24-81SystemVerilog Testbench ConstructsA default constraint for a particular variable is deemed applicable if no other non-default constraints apply t

24-82SystemVerilog Testbench Constructs• A default constraint block can be defined externally (that is, in a different file from the one in which the

24-83SystemVerilog Testbench ConstructsA default constraint does not override other default constraints under any condition. Thus, if you declare all

2-37Modeling Your Designmodule top; middle u1 (a); endmodulemodule middle(a); input a; wire b; buf(b,a); endmoduleFirst, there is no instance name spe

24-84SystemVerilog Testbench Constructsinitial beginD d = new();d.y = 1;d.randomize();d.y = 0;d.randomize();endendprogramIn the example, the default c

24-85SystemVerilog Testbench ConstructsOutputx = 10 y = 0In the example, x = 10 since only the second constraint in the default constraint block is ov

24-86SystemVerilog Testbench ConstructsOutput:First call to randomize,the guard g evaluates to FALSEx = 9 y = 1 g = 0Second call to randomize,the guar

24-87SystemVerilog Testbench ConstructsOutput First call to randomize, rand mode of x and y are ON x = 3 y = 7 Second call to randomize, rand mode of

24-88SystemVerilog Testbench ConstructsUnidirectional ConstraintsThe current extension to the constraint language allows the specification of partitio

24-89SystemVerilog Testbench ConstructsThe $void() function imposes an ordering among the variables. All parameters to $void() function calls in a con

24-90SystemVerilog Testbench Constructs}Figure 24-1Figure 24-1 illustrates the dependencies between the variables. The variable y must be solved befo

24-91SystemVerilog Testbench Constructs• Can r be solved at the same time as x?Consider x !=(y+r) again. Figure 24-1 illustrates that the relationship

24-92SystemVerilog Testbench Constructs• A void() function being applied to a sub-expression of the parameter of another void() function (for example,

24-93SystemVerilog Testbench Constructs2. The constraint is solved when the lowest priority variables incident on it are solved.3. When the constraint

2-38Modeling Your Design$lsi_dumpports(test.u0.u1,"dump.out2"); end top u0 (a); endmodulemodule top(a); input a; middle u1 (a); endmodulemod

24-94SystemVerilog Testbench Constructs2. x is solved using the constraints: x%y == 0; x!=y;3. z is solved using the constraint: z ==x*y;The sequence

24-95SystemVerilog Testbench ConstructsSemantics of solve-before construct without the hard modifierThe solve-before constraints that are not modified

24-96SystemVerilog Testbench Constructsclass B; rand integer x[$]; rand bit[1:0] k; constraint b1 { x.size() == k; k != 2; foreach(x, i) { $void(k-1)

24-97SystemVerilog Testbench Constructs3. The loop is expanded and all the members of the x array are solved for.The semantics of array constraints in

24-98SystemVerilog Testbench Constructs1. y is solved using the constraint y inside {0,1}.2. z, x are solved using the default constraint x<=y and

24-99SystemVerilog Testbench ConstructsHowever, when unidirectional constraints are used in the presence of randc variables, it is possible that rand

24-100SystemVerilog Testbench ConstructsRandomize Methodsrandomize()Variables in an object are randomized using the randomize() class method. Every cl

24-101SystemVerilog Testbench Constructsconstraint con_size {s > 0;s < 50;}endclassclass Pkt; integer header[7];rand bit [7:0] payload[]; size s

24-102SystemVerilog Testbench Constructsinteger success,i; initial beginpkt = new(); //instantiate pktfor (int j = 0; j < 5; j++)beginsuccess = pkt

24-103SystemVerilog Testbench ConstructsSyntax:task object[.constraint_identifier]::constraint_mode(bit ON | OFF);orfunction int object.constraint_ide

2-39Modeling Your DesignHhighX unknown (don’t care)Ttristatel low (2 or more DUT drivers active)Testbench Level (only z drivers from the DUT)h high (2

24-104SystemVerilog Testbench Constructs else $display("Error with constraint_mode");generateRandomAddresses(`N);// turn O

24-105SystemVerilog Testbench Constructsbb.addr = 36593bb.addr = 19491bb.addr = 6853bb.addr = 48017=========one constraint ON =======bb.addr = 11b

24-106SystemVerilog Testbench Constructsfunction int object.randvar_identifier::rand_mode();rand_mode() returns -1 if the specified variable does not

24-107SystemVerilog Testbench ConstructsgenerateRandomAddresses(`N);// turn OFF "data" random variable in "bb"bb.data.rand_mode(0)

24-108SystemVerilog Testbench Constructsbb.addr = 121,, bb.data = 219bb.addr = 121,, bb.data = 219bb.addr = 121,, bb.data =

24-109SystemVerilog Testbench Constructs repeat (10) begin int1 = bus.randomize() with {bitrand1[1:0] == 2'b00;}; if (int1 ==

24-110SystemVerilog Testbench ConstructsThe following example illustrates the usage of in-line constraint checker.program test;class myclass; rand

24-111SystemVerilog Testbench ConstructsRandom Number GenerationSystemVerilog includes a number of system functions to work with random numbers. Some

24-112SystemVerilog Testbench Constructs $display("Generation of random number with seed 3 :"); a = $urandom(3); b = $u

24-113SystemVerilog Testbench Constructs a = 10; a1 = 3; $display("Generating random numbers with urandom_range with expressions

2-40Modeling Your Design

24-114SystemVerilog Testbench ConstructsProviding the same seed ensures that the same set of random values are generated by the random number generato

24-115SystemVerilog Testbench ConstructsThe output of this program is:Setting the seed as 2 through srandoma = 8, b = 3a = 14, b = 3Changing the seed

24-116SystemVerilog Testbench Constructsd3 = a.x;a.srandom(r);d1 = a.randomize();if(d1 == 1)d4 = a.x;if((d2 == d4) && (d2 != d3))$display(&quo

24-117SystemVerilog Testbench Constructs randcase a+3 : count_2++; // simple add expression as weight 10 : count_c++; // constant

24-118SystemVerilog Testbench ConstructsSystemVerilog’s sequence generation allows you to specify the syntax of valid sequences using BNF-like notatio

24-119SystemVerilog Testbench ConstructsNote:Nesting of randsequence blocks is not supportedWhen the randsequence block is executed, random production

24-120SystemVerilog Testbench Constructs The syntax for rs_production_list is: rs_prod{rs_prod} | rand join [(expression)] production_item product

24-121SystemVerilog Testbench ConstructsA randsequence block is made up of one or more productions, yielding a “production list.” Productions are made

24-122SystemVerilog Testbench Constructs F : {$write ("F");}; G : {$write ("G");}; endsequenceendendprogram Production Co

24-123SystemVerilog Testbench Constructsweight_specificationThe syntax for weight_specification is:integral_number | ps_identifier | (expression)The e

3-1Compiling and Elaborating Your Design3Compiling Your Design 1VCS compiles your design before simulation. You can use the vcs command to compile you

24-124SystemVerilog Testbench ConstructsIf the conditional evaluates to true, the first production item is selected. If it evaluates to false, the sec

24-125SystemVerilog Testbench Constructscase StatementsA general selection mechanism is provided by the case statement. The syntax to declare a case s

24-126SystemVerilog Testbench Constructsrepeat LoopsThe repeat loop is used to loop over a production a specified number of times. The syntax to decla

24-127SystemVerilog Testbench ConstructsSyntax break;A break statement can be executed from within an rs_code_block within a production definition. Wh

24-128SystemVerilog Testbench ConstructsAspect Oriented ExtensionsThe Aspect oriented extensions is a Limited Customer availability (LCA) feature in N

24-129SystemVerilog Testbench Constructsmethodology. AOP is a way of modularizing such cross-cutting concerns. AOP extends the functionality of existi

24-130SystemVerilog Testbench ConstructsFor information on the creation and refinement of verification testbenches, see the Reference Verification Met

24-131SystemVerilog Testbench ConstructsAn extends directive for a class defines a scope in SV language. Within this scope exist the items that modify

24-132SystemVerilog Testbench ConstructsProcessing of AOE as a Precompilation Expansion As a precompilation expansion, AOE code is processed by VCS to

24-133SystemVerilog Testbench ConstructsSyntax:extends_directive ::=extends extends_identifier (class_identifier)[dominate_list]; extends_item_listend

ixNavigating the Design and Displaying Design Information . . 9-2Showing and Retrieving Simulation Information . . . . . . . . . . 9-4Setting, Displa

3-2Compiling and Elaborating Your Design• Initializing Memories and Regs• Initializing Memories and Regs• Allowing Inout Port Connection Width Mismatc

24-134SystemVerilog Testbench Constructs stmt ::= statement | proceed ;hide_list ::=hide([hide_item {,hide_item}]);hide_item

24-135SystemVerilog Testbench Constructsaspects are added to the class definition. It also determines the order in which advices defined in the aspect

24-136SystemVerilog Testbench Constructsopt_method_specifiersRefers to a combination of protection level specifier (local, or protected), virtual met

24-137SystemVerilog Testbench Constructselement could be any of the keywords, before, after, or around, and the advices with these placement elements

24-138SystemVerilog Testbench ConstructsThe following table shows the rest of the steps involved in weaving of the advice for each type of placement e

24-139SystemVerilog Testbench ConstructsAdvice:before task myTask (); $display("Before in aoe1\n");endtaskWeaving of the advice in the targe

24-140SystemVerilog Testbench ConstructsWeaving of the advice in the target method yields the following. task myTask_newTarget(); myTask();myTa

24-141SystemVerilog Testbench ConstructsWeaving of the advice in the target method yields the following. task myTask_around(); $display("A

24-142SystemVerilog Testbench ConstructsWeaving of the advice in the target method yields: task myTask_around(); myTask();$display("Around

24-143SystemVerilog Testbench Constructs5. Weaving of all advices in the input program are weaved into their respective class methods as per the prece

3-3Compiling and Elaborating Your DesignFor a complete description of the syntax of the vcs command, see Appendix B, "Compile-Time Options".

24-144SystemVerilog Testbench Constructsclass packet; ...// Other member fields/methods...task send(); $display("Sending data\n");endtas

24-145SystemVerilog Testbench Constructssince aspect_3 is coded later in Input.vr than aspect_2, aspect_3 has higher precedence than aspect_2. Therefo

24-146SystemVerilog Testbench ConstructsWeaving of advicesAn input program may contain several aspect extensions for any or each of the different clas

24-147SystemVerilog Testbench Constructsother in the sense that their relative precedence to each other does not affect their relative order of execut

24-148SystemVerilog Testbench Constructs$display("Aspect_2: send advice after\n");endtaskendclassextends aspect_1(packet) dominates (aspect_

24-149SystemVerilog Testbench Constructs...task send(); $display("Sending data\n”);endtasktask send_Created_a();send();send_after_Created_b();end

24-150SystemVerilog Testbench Constructscall to send_Created_a. At the end of this step, send_around_Created_c becomes the new target method for weavi

24-151SystemVerilog Testbench Constructsendtaskendextends// End of file Input.svThis Example 24-14 shows what the input program looks like after weavi

24-152SystemVerilog Testbench Constructs$display("Aspect_2: send advice after\n");endtasktask send_around_Created_c(); send_before_Created_d

24-153SystemVerilog Testbench Constructs// Begin file input.vrprogram top; foo f;f = new();f.myTask();endprogramclass foo; int i;task myTask();$displa

3-4Compiling and Elaborating Your DesignCompile-time options that affect incremental compilation all begin with -M. For more details on these options,

24-154SystemVerilog Testbench Constructsf = new();f.myTask();endprogramclass foo; int i;task myTask(); printf("Executing original code\n");e

24-155SystemVerilog Testbench ConstructsBecause advices are woven after introductions have been added to the class definitions, advices can be specifi

24-156SystemVerilog Testbench Constructsbefore task foo(integer x); x = 99; //force every call to foo to use x=99endtaskendextends// End file exampl

24-157SystemVerilog Testbench ConstructsWhen executed, the output of the program code is:Point 1: Value = 5Point 2: Value = 5Point 3: Value = 6Output

24-158SystemVerilog Testbench ConstructsExample 24-19class pbase; virtual task print(); $display("I’m pbase\n");endtaskendclassclass packet

24-159SystemVerilog Testbench Constructsb. Permission to suspend access rules and to specify advice that changes protected and local virtual methods (

24-160SystemVerilog Testbench Constructsclass packet extends pbase;task foo();$display(); endtasklocal virtual task rules-test();$display("Rules-

24-161SystemVerilog Testbench ConstructsExample 24-21 is shows how AOE can be used to introduce new members into a class definition. myaspect adds a n

24-162SystemVerilog Testbench Constructsconstraint con1 {myfield == 4;}endextendsExamples of advice codeIn Example 24-23, the extends directive adds a

24-163SystemVerilog Testbench ConstructsIn Example 24-24, extends directive myaspect adds advice to turn off constraint c1 before each call to the foo

3-5Compiling and Elaborating Your DesignUsing Shared Incremental CompilationShared incremental compilation allows a team of designers working on a la

24-164SystemVerilog Testbench ConstructsExample 24-26// Begin file example.svprogram test; packet p;p = new();p.setLen(5000);p.send();p.setLen(10000);

24-165SystemVerilog Testbench ConstructsArray manipulation methodsVCS-NTB provides the following types of built-in methods for analyzing and manipulat

24-166SystemVerilog Testbench Constructssort()The sort() method sorts the element in an ascending order using the expression in the with construct. Th

24-167SystemVerilog Testbench ConstructsIn the first example the elements in the queue1 are sorted in descending order of their values provided they a

24-168SystemVerilog Testbench ConstructsExample 24-30queue2 = queue1.find() with (queue1.leg() > 5);In the example, queue1 contains a set of string

24-169SystemVerilog Testbench Constructsfunction array_type[$] array_name.first() with (expression);Example 24-32value = queue1.first() with (item >

24-170SystemVerilog Testbench Constructsfind_last()The find_last() method returns a queue with the last element satisfying the expression. If the arra

24-171SystemVerilog Testbench ConstructsIn the first example, the index of the last element which is greater than 5 is returned. In the second example

24-172SystemVerilog Testbench ConstructsSyntaxfunction array_type[$] array_name.max() [with (expression)];Example 24-37value = array1.max();object = a

24-173SystemVerilog Testbench Constructsunique_index()The unique_index()method returns the indexes of all elements with unique values or whose express

3-6Compiling and Elaborating Your DesignThe chip designer needs to know what debug features the board designer needs in the chip design. The chip desi

24-174SystemVerilog Testbench ConstructsExample 24-40value = Qint.sum(); // Calculates sum of all elementsvalue = QPacket.sum() with (item.pkt_size);

24-175SystemVerilog Testbench Constructsand() The and() method computes the bitwise AND (&) of all the array elements for integral types. The with

24-176SystemVerilog Testbench ConstructsExample 24-43value = Qint.or(); // Calculates sum of all elementsvalue = QPacket.or()with (item.pkt_size ); //

24-177SystemVerilog Testbench ConstructsInterprocess Synchronization and CommunicationSemaphoresSystemVerilog semaphores are not signal devices. They

24-178SystemVerilog Testbench ConstructsThe program has a semaphore named sem1 that starts with two keys, as specified with the semaphore keyword and

24-179SystemVerilog Testbench Constructs #5 sem1.put(1); $display("inital2 returns 1 key at %0t",$time); endendprogramIn the revised

24-180SystemVerilog Testbench Constructsget(number_of_keys)Decrements the number of keys in the semaphore. If there aren’t the specified number of key

24-181SystemVerilog Testbench Constructs endi = mbx.num();repeat (3) begin #5 $display("No. of msgs in mbx = %0d j = %0d at %0t",

24-182SystemVerilog Testbench ConstructsMailbox MethodsMailboxes use the following methods:new()Along with the mailbox keyword, declares a new mailbox

24-183SystemVerilog Testbench Constructstry_peek(variable)Assigns the value of the first message to the variable without removing the message. If the

3-7Compiling and Elaborating Your DesignThe board designer includes the -Mdir option to specify a directory where VCS writes the generated files for t

24-184SystemVerilog Testbench Constructstask t1;event evt1;#5 -> evt1;endtaskinitialt1;initial@(t1.evt1) $display("t1.evt1 happened at %0t&quo

24-185SystemVerilog Testbench Constructsfork -> evt2; begin wait (evt2.triggered); $display("evt2 occurred"); endjoinendp

24-186SystemVerilog Testbench Constructsinitial#1 @ (evt3) $display("evt3 triggerred");endprogramThe $display system tasks display the follo

24-187SystemVerilog Testbench Constructs#1 @(evt1) $display("evt1 triggered");initialbegin#5 wait (evt1.triggered);$display("evt1 occur

24-188SystemVerilog Testbench Constructsevt1 === evt2evt1 != evt3evt3 != nullIn comparing named events, the case equality operator === works the same

24-189SystemVerilog Testbench Constructsclocking_identifierName of the clocking block being declared.clocking_eventEvent that acts as the clock for th

24-190SystemVerilog Testbench Constructsclocking_skewDetermines how long before the synchronized edge the signal is sampled, or how long after the syn

24-191SystemVerilog Testbench Constructsinput #1 i1;where i1 is the signal_identifier.Note: A clocking block signal can only be connected to a scalar,

24-192SystemVerilog Testbench Constructsreg out3;reg out1;reg clk = 0;p1 p(out3,clk,out1);assign out1 = out3;initial forever begin clk = 0;

24-193SystemVerilog Testbench Constructs endendprogramThe output of this program is: 0 x 30 0 130 0150 1Inpu

3-8Compiling and Elaborating Your DesignInitializing Memories and RegsVCS has compile-time options for initializing all bits of memories and regs to t

24-194SystemVerilog Testbench ConstructsHierarchical ExpressionsEvery signal in a clocking block is associated with a program port or a cross module r

24-195SystemVerilog Testbench ConstructsendclockingClocking blocks that use the same clock can share the same synchronization event. For example:progr

24-196SystemVerilog Testbench ConstructsClocking Block EventsThe clocking_identifier can be used to refer to the clocking_event of a clocking block.

24-197SystemVerilog Testbench ConstructsNote:You can specify only one default clocking block in a program, module, or interface. VCS issues a compilat

24-198SystemVerilog Testbench ConstructsAny SystemVerilog expression that evaluates to a positive integer value.For example:## 2;## (x+1);Note:VCS iss

24-199SystemVerilog Testbench ConstructsSynchronous EventsThe event control operator, @, is used for explicit synchronization. This operator causes a

24-200SystemVerilog Testbench Constructsinitialbegin@ (cb1); //synchronising with clocking eventcb1.a <= 0; //drive at first posedgecb1.b <= 0;

24-201SystemVerilog Testbench Constructssequence seq ; @(ck1) a ##1 b ;endsequenceA: assert property (@(ck1) a ##1 b) ;N: assert property (seq) ;In t

24-202SystemVerilog Testbench ConstructsSystemVerilog Assertions Expect StatementsSystemVerilog assertions expect statements differ from assert, assum

24-203SystemVerilog Testbench ConstructsThe following is an example of an expect statement:e1: expect (@(posedge clk) ##1 in1 && in2)

3-9Compiling and Elaborating Your Design• Assigning values to regs or memory elements at simulation time 0 when the value you assign is not the same a

24-204SystemVerilog Testbench Constructscalled the success block. if false VCS executes the second action blockafter the keyword else, called the fail

24-205SystemVerilog Testbench Constructs[*] is the consecutive repeat operator. This expect statement calls for waiting a clock delay and then seeing

24-206SystemVerilog Testbench Constructs else begin bit1=0; $display("failure at %0t in %m\n",$time);

24-207SystemVerilog Testbench Constructssuccess at 125 in test.tbpb1.e3Virtual InterfacesA Virtual Interface (VI) allows a variable to be a dynamic re

24-208SystemVerilog Testbench ConstructsScope of SupportVCS supports virtual interface declarations in the following locations:• program blocks and cl

24-209SystemVerilog Testbench Constructswriting assignments are subject to modport direction enforcement so that, for example, “sb.req = 1" would

24-210SystemVerilog Testbench Constructsinterface intf(input clk); int d; clocking cb @(posedge clk); default input #2 output #2; in

24-211SystemVerilog Testbench ConstructsIn the above example, if the modport passed to the testbench is of asynchronous type “intf.master” then the pr

24-212SystemVerilog Testbench Constructsprogram p; virtual intf VI[3:0]; initial begin VI = top.INTF; //aggregate assignment

24-213SystemVerilog Testbench Constructsendinterface...program P;virtual SyncBus vi;...initial vi.cb.w <= 1;...endprogramIn this case the assignme

3-10Compiling and Elaborating Your DesignWithout the +noerrorIOPCWM compile-time option, VCS displays the following error message and does not create

24-214SystemVerilog Testbench Constructsbegin virtual I vi; vi.data <= 1;end• NULL assignmentvirtual I vi = NULL;Not Yet Implemented • Named typ

24-215SystemVerilog Testbench ConstructsVCS collects all the coverage data during simulation and generates a database. VCS provides a tool to read the

24-216SystemVerilog Testbench ConstructsendprogramThis program contains the following:• The enumerated data type colors, with members named red, blue,

24-217SystemVerilog Testbench ConstructsDefining a Coverage PointIn a coverage point definition you can specify the following:• bins for value ranges•

24-218SystemVerilog Testbench ConstructsCoverage point data will have 20 bins, the first named some_name_1 and the last named some_name_20.Bin Value/

24-219SystemVerilog Testbench ConstructsExample :bit [1:0] cp_exp1;// type evaluates to the value range of 0 to 3bit signed [2:0] cp_exp2;// type eval

24-220SystemVerilog Testbench ConstructsYou can specify different bins for different value ranges, for example:coverpoint data {bins first_ten = {[1:1

24-221SystemVerilog Testbench ConstructsHere the information about when data is 0, 1, 2, 3, 5, 7, 9, and 10 is in bin1, the information about when dat

24-222SystemVerilog Testbench ConstructsYou can use range lists to specify more than one starting value and more than one ending value, for example:bi

24-223SystemVerilog Testbench Constructs}VCS displays an error message when the coverage point reaches these values or makes these transitions.Definin

3-11Compiling and Elaborating Your DesignVCS displays this message when you attach an entire vector reg instead of a bit-select to an input terminal o

24-224SystemVerilog Testbench ConstructsIn covergroup cg1 there are two coverpoints labeled bit1 and bit2. In addition, there is the following:1. the

24-225SystemVerilog Testbench ConstructsThe binsof construct supplies the coverage bins for the expression argument, which can be either a coverpoint

24-226SystemVerilog Testbench ConstructsSimilarly, cross bin, bin2 receives data whenever either bin hicp1vals, of coverpoint cp1, receives data, or b

24-227SystemVerilog Testbench ConstructsNote: In cumulative mode, only cumulative information can be queried for. Furthermore, the coverage reports

24-228SystemVerilog Testbench Constructstype_option.weight = integer;Specifies the weight of the covergroup when calculating the overall coverage. Spe

24-229SystemVerilog Testbench Constructscg1 cg1_1 = new;initial begin cg1_1.option.weight = 10; cg1_1.option.goal = 75;...endInstance specific optio

24-230SystemVerilog Testbench ConstructsPredefined Coverage MethodsSystemVerilog provides a set of predefined covergroup methods described in this sec

24-231SystemVerilog Testbench Constructs bins s0 = {[ 0 : 2]} ; bins s1 = { 3 }; bins s2 = { 4 }; bins s3 = { 5 };

24-232SystemVerilog Testbench Constructsvar=111 coverage=83.333336var=000 coverage=100.000000var=001 coverage=100.000000var=010 coverage=100.000000var

24-233SystemVerilog Testbench Constructs endendinitial cov1 = new(2);endprogramThe output of the program is:va1r=010 coverage=0.000000va1r=011 co

xDebugging Simulation Mismatches . . . . . . . . . . . . . . . . . . . . 11-10The Static Race Detection Tool . . . . . . . . . . . . . . . . . . . . .

3-12Compiling and Elaborating Your Design• Disable all lint messages. This is the default.+lint=noneThe syntax of the +lint option is very similar to

24-234SystemVerilog Testbench Constructsinitialbegin cov1 = new(2); $display("Original instance name is %s\n", cov1.option.name); cov

24-235SystemVerilog Testbench ConstructscovType cov1;initial cov1 = new();initial begin repeat (10) begin #10 clk = ~clk; var = var

24-236SystemVerilog Testbench Constructs bins s2 = { 4 }; bins s3 = { 5 }; bins s4 = { 6 }; bins s5 = { 7 }; }endgroupc

24-237SystemVerilog Testbench Constructsvar=111 covergae=0.000000var=000 covergae=16.666666var=001 covergae=33.333332var=010 covergae=33.333332var=011

24-238SystemVerilog Testbench ConstructsThe Coverage ReportDuring simulation VCS creates a default database directory simv.vdb. For the code example a

24-239SystemVerilog Testbench ConstructsTotal 3 3 100.00 cp1 3 3 100.00 100 1 ----------

24-240SystemVerilog Testbench ConstructsThe HTML FileThe command to instruct VCS to generate a coverage report in HTML format is:urg -dir simv.vdbThis

24-241SystemVerilog Testbench ConstructsPersistent Storage of Coverage Data and Post-Processing Tools Unified Coverage Directory and Database ControlA

24-242SystemVerilog Testbench ConstructsTable 24-5 Unique Name Generation SchemeYou can disable this method of ensuring database backup and force VCS

24-243SystemVerilog Testbench ConstructsLoading Coverage DataBoth cumulative coverage data and instance-specific coverage data can be loaded. The load

3-13Compiling and Elaborating Your Design• -pvalue• -parametersYou specify a parameter with the -pvalue option. It has the following syntax:vcs -pvalu

24-244SystemVerilog Testbench ConstructsIn the Example 1-1, below, there is a SystemVerilog class MyClass with an embedded covergroup covType. VCS fin

24-245SystemVerilog Testbench ConstructsThe commands above direct VCS to find the coverage data for the specified instance name in the database, and l

24-246SystemVerilog Testbench Constructs-cm_name filenameAs a compile-time or runtime option, specifies an alternative test name instead of the defaul

24-247SystemVerilog Testbench ConstructsfilenameName of the file where the memory profiler dumps the report.w | a+w and a+ designate the mode in which

24-248SystemVerilog Testbench Constructsvcs -ntb -sverilog +dmprof dut_filename.v testbench_filename.sv \[-debug | -debug_all]Note: Use the -sverilo

24-249SystemVerilog Testbench Constructsinteger arr1[*];arr1 = new[500];delay(5);}task t2() {integer arr2[*];arr2 = new[500];delay(10);} program main

24-250SystemVerilog Testbench Constructs3. Program View Reports the dynamic memory consumed in each SV program in the system.4. Program To Construct V

24-251SystemVerilog Testbench ConstructsThe Direct Programming Interface (DPI)The Direct Programming Interface (DPI) is a Limited Customer availabilit

24-252SystemVerilog Testbench ConstructsExample:import "DPI" context task c_task(input int addr);program top; initial c_task(1000); initia

24-253SystemVerilog Testbench ConstructsExample:import "DPI" task c_test(int addr);initial c_task(1000);export "DPI" task sv_add;f

3-14Compiling and Elaborating Your DesignNote:The -parameters and -pvalue options do not work with a localparam or a specparam.Checking for X and Z Va

24-254SystemVerilog Testbench Constructs• The main include file, $VCS_HOME/lib/svdpi.h, is defined in the SystemVerilog 3.1 standard and defines the c

24-255SystemVerilog Testbench ConstructsTime Consuming Blocking Tasks When SystemVerilog calls a C import task, this task can then call blocking (cont

24-256SystemVerilog Testbench ConstructsSystemVerilog FileThis SV code calls C_test(), which then calls the blocking APB_Write task in SystemVerilog.

25-1Source Protection25Source Protection 1Source protection changes the source description of a Verilog model so that others cannot read or understand

25-2Source Protection• Creating a VMC model from source description:A VMC model is an executable binary that you compile from your Verilog model. To s

25-3Source ProtectionEncrypting Source FilesEncrypt Using Compiler DirectivesYou use compiler directives and command line options to encrypt source an

25-4Source ProtectionEncrypting Specified RegionsYou can control what part of your source VCS encrypts in the new files and which part remains readabl

25-5Source Protectionalwaysbegin:counter`protect //begin protected regionreg [7:0] int;count = 0;int = inp;while (int)beginif (int [0]) count = c

25-6Source ProtectionTo do so include the +autoprotect, +auto2protect or +auto3protect option on the vcs command line. The difference between these op

25-7Source Protection• VCS inserts the ‘protected compiler directive after the module header and the ‘endprotected compiler directive before the endmo

3-15Compiling and Elaborating Your DesignVCS displays this warning every time it evaluates the conditional expression to have an X or Z value, not jus

25-8Source ProtectionCB75+Q/]R_IAP/>HS+b<XFP,-BHfcZTIG0-QILLIa1#.RbX6.K?Oc8f5]f);BW=QFVa@-^&@e+:K0>(?(&ZL:4Z:.F[<5J)gQ+CaA]^7\.N^/

25-9Source ProtectionEncrypting SDF FilesTo create a new SDF file with encrypted content include, on the vcs command line, the +sdfprotect option with

25-10Source ProtectionSpecifying Encrypted Filename ExtensionsYou can specify a different extension for the new filenames by adding the new extension

25-11Source Protection• If the encrypted file already exists, VCS outputs an error message and does not overwrite the existing file. This error messag

25-12Source ProtectionSimulating Encrypted ModelsWhen you simulate an encrypted model, information about hierarchical names and design objects is prot

25-13Source ProtectionSome CLI commands whose arguments are design objects continue to work but only if you know the hierarchical name of the object.

25-14Source Protectionif (acc_object_of_type(obj, accProtected)) {printf("object %s is from a protected module\n",acc_fetch_name(obj));}If t

25-15Source ProtectionYou can substitute -Xman for -Xmangle. The argument number can be 1 or 4: -Xman=1Randomly changes names and identifiers to provi

25-16Source ProtectioninData35=iPb[cpuTmpCnt];$display("\tiPb[%0h]=%b, %h", cpuTmpCnt,iPb[cpuTmpCnt],iPb[cpuTmpCnt] >> 3);cpuDatareg=m

25-17Source Protectioninitial beginWfmoe = 256’b0;for (Ifmoe = 0; (Ifmoe < 8); Ifmoe = (Ifmoe + 1)) begin : Bimoereg [0:34] Timoe;Timoe = Sfmoe[Ifm

3-16Compiling and Elaborating Your DesignFiltering Out False NegativesBy default, if a signal in a conditional expression transitions to an X or Z val

25-18Source Protectionreg [0:255] source_line;reg [0:31] source_word;reg [0:2] word_index;beginendendfunctioninitial begin cpuDatareg = 256’b0; for

25-19Source Protectioninput[7:0] modulus1;output[255:0] cpuData;integer cpuTmpCnt;reg [255:0] cpuDatareg;reg [0:34] iPb[0:10];assign cpuData = cpuData

25-20Source ProtectionHere there are additional comments about the system tasks used and the source file and line number of the module header.The foll

25-21Source Protection cpuDatareg = 256’b0; for (cpuTmpCnt = 0; (cpuTmpCnt < 8); cpuTmpCnt = (cpuTmpCnt + 1)) begin : assemble_incoming reg[

25-22Source Protection// No. of user function calls: 0 0// No. of hierarchical references: 0 0//

25-23Source ProtectionCreating A Test CaseHere is a quick way to create a small test case:1. Remove -o option if you are using it.2. Add the-Xman=4

25-24Source Protectionb. At the Name prompt, enter anonymous.At the Password prompt, enter your e-mail address.c. At the ftp> prompt enter:cd incom

25-25Source ProtectionThe -Xnomangle option should only be used on top level modules, i.e., ones that are not called by any other module in the design

25-26Source Protection

A-1VCS Environment VariablesAVCS Environment Variables AThere are a number of variables you use to set up the simulation environment in VCS.This appen

3-17Compiling and Elaborating Your DesignExample 5 False Negative Examplemodule test;reg r1;initialbeginr1=1'b0;#1 r1<=1'b1;r1=1'bx;

A-2VCS Environment VariablesSimulation Environment VariablesERROR_WHEN_UNBOUNDTo run VCS, you need to set the following basic environment variables:$V

A-3VCS Environment VariablesOptional Environment VariablesVCS also includes the following environment variables that you can set in certain circumstan

A-4VCS Environment VariablesVCS_LIC_EXPIRE_WARNINGBy default VCS displays a warning 30 days before a license expires. You can specify that this warnin

B-1Compile-Time OptionsBCompile-Time Options BThe vcs command performs compilation of your designs and creates a simulation executable. Compiled event

C-2Compile-Time Optionssource_or_object_filesOptional C files (.c), object files (.o), or archived libraries (.a). These are DirectC or PLI applicatio

C-3Compile-Time Options• Options for 64-bit Compilation• Options for Debugging• Options for Finding Race Conditions• Options for Starting Simulation R

C-4Compile-Time Options• Options for Controlling Messages• Options for Cell Definition• Options for Licensing• Options for Controlling the Assembler•

C-5Compile-Time OptionsVCS looks in this directory for a file with the same name as the module or UDP identifier in the instance (not the instance nam

C-6Compile-Time Optionsin a source file in a Verilog library directory that resolves a module instantiation statement that VCS read in your source fil

C-7Compile-Time Optionsargument specifies the default condition, which is incremental compilation and updating the makefile.-Mdefine=name=valueAdds a

3-18Compiling and Elaborating Your Design r1 false at 1 r1 true at 1If you compile and simulate example1 or example2 with the -xzcheck compile-time op

C-8Compile-Time Optionsvcs design.v -Mlib=/design/dir1 -Mlib=/design/dir2Or you can specify more than one directory with this option, using a colon (:

C-9Compile-Time Options-Mlib option, the -Mrelative_path option does not expand the relative path to an absolute path on the linker line in the make f

C-10Compile-Time Options-ignore keyword_argumentSuppresses warning messages depending on which keyword argument is specified. The keyword arguments ar

C-11Compile-Time OptionsdumpoffDisables the dumping of SVA information in the VPD file during simulation.vpiSeqBeginTimeEnables you to see the simulat

C-12Compile-Time Options-ntb_filext .extSpecifies an OpenVera file name extension. You can specify multiple file name extensions using the plus (+) ch

C-13Compile-Time Optionsprint_depsTells VCS to display the dependencies for the source files on the screen or in the specified file. Enter this argume

C-14Compile-Time Options...);Without vera_portname, the Vera shell module name is based on the name of the OpenVera program by default. Bind signals a

C-15Compile-Time Optionsfiles for processing in OpenVera encrypted IP mode. Unlike the -ntb_filext option, the default encrypted-mode extensions .vrp,

C-16Compile-Time OptionsOptions for Initializing Memories and Regs+vcs+initmem+0|1|x|zInitializes all bits of all memories in the design. See “Initial

C-17Compile-Time OptionsOptions for Debugging-lineEnables source-level debugging tasks such as stepping through the code, displaying the order in whic

3-19Compiling and Elaborating Your Design• designs with extensive use of timing such as delays, timing checks, and SDF back annotation, particularly t

C-18Compile-Time Options+cli+4Same as above, plus enables force and release of registers.Using these options also creates the Direct Access Interface

C-19Compile-Time Options5. Enter the FTP command bin.6. Enter the FTP command get readline-2.0.tar.gz. This downloads the file to your current directo

C-20Compile-Time Options+acc or +acc+1Enables all capabilities except breakpoints and delay annotation.+acc+2Above, plus breakpoints+acc+3Above, plus

C-21Compile-Time Options+race=allAnalyzes the source code during compilation to look for coding styles that cause race conditions. See “The Static Rac

C-22Compile-Time OptionsOptions for Compiling OpenVera Assertions (OVA)-ovacStarts the OVA compiler for checking the syntax of OVA files that you spec

C-23Compile-Time Options-ova_inlineEnables compiling of OVA code that is written inline with a Verilog design.-ova_lintEnables general rules for the O

C-24Compile-Time OptionsfsmCompile for FSM coverage.tglCompile for toggle coverage.pathCompile for path coverage.branchCompile for branch coverageasse

C-25Compile-Time OptionsfullLogical and non-logical, multiple conditions, no sensitized conditions.allopsLogical and non-logical conditions.eventSigna

C-26Compile-Time Options- In FSM coverage, reports not just whether an FSM reached a state, and had such a transition, but also the number of times it

C-27Compile-Time OptionsoptimistSpecifies identifying illegal transitions when VCS extracts FSMs in FSM coverage. cmView then reports illegal transiti

3-20Compiling and Elaborating Your DesignMaking Accessing an Out of Range Bit an Error ConditionBy default it is a warning condition if your code assi

C-28Compile-Time Optionsto either exclude from coverage or exclusively compile for coverage. -cm_ignorepragmasTells VCS to ignore pragmas for coverage

C-29Compile-Time Optionsgui Tells VCS to start the cmView graphical user interface to display coverage data.batchTells VCS to start cmView to write re

C-30Compile-Time Options-cm_tgl mdaEnables toggle coverage for Verilog-2001 multidimensional arrays (MDAs) and SystemVerilog unpacked MDAs. Not requir

C-31Compile-Time Options-assert dveEnables SystemVerilog assertions tracing in the VPD file. This tracing enables you to see assertion attempts.Note:T

C-32Compile-Time OptionsOptions for Specifying Delays +allmtmSpecifies enabling the simv executable for the +mindelays, +typdelays, or +maxdelays opti

C-33Compile-Time Options‘timescale compiler directives in the source code. The default time unit and time precision argument of the ‘timescale compile

C-34Compile-Time OptionsThese delays impede the simulation performance of the design so after debugging you can remove these delays with this option.N

C-35Compile-Time OptionsOptions for Compiling an SDF File+allmtmSpecifies compiling separate files for minimum, typical, and maximum delays when there

C-36Compile-Time Optionstriplets when compiling the SDF file. See “Min:Typ:Max Delays” on page 13-37. The mtm_spec argument to the $sdf_annotate syste

C-37Compile-Time OptionsAs an alternative to using this option, you can use the ‘vcs_mipdexpand compiler directive or you can enter the mipb ACC capab

3-21Compiling and Elaborating Your Design"source_file.v", line_number: signal[bit]Like the warning message, the error message includes the m

C-38Compile-Time OptionsOptions for File Containing Source File Names and Options-f filenameSpecifies a file name that contains a list of absolute pat

C-39Compile-Time Options-file filenameThis option is for problems you might encounter with entries in files specified with the -f or -F options. This

C-40Compile-Time OptionsOptions for Pulse Filtering +pulse_e/numberDisplays an error message and propagates an X value for any path pulse whose width

C-41Compile-Time Optionsuntil the short pulse propagates through the module or until another simulation event drives a value on the output port. See “

C-42Compile-Time OptionsOptions to Enable and Disable Specify Blocks and Timing Checks+pathpulseEnables the search for the PATHPULSE$ specparam in spe

C-43Compile-Time Optionsdisplay of warning messages when VCS finds a timing violation that you specified in a timing check.+no_tchk_msgDisables displa

C-44Compile-Time Optionsthe signals in the $setuphold and $recrem timing checks. See “Other Timing Checks Using the Delayed Signals” on page 14-14.+NT

C-45Compile-Time Options+vcs+flush+fopenIncreases the frequency of flushing all the buffers for the files opened by the $fopen system function.+vcs+fl

C-46Compile-Time Optionsinstantiation statement that VCS read in your source files, a library file, or in another file in a library directory. The mes

C-47Compile-Time Options-VtVerbose mode; provides CPU time information. Like -V, but also prints the amount of time used by each command. Use of the -

xiDisabling CELLTYPE Checking in SDF Files . . . . . . . . . . . . 13-15The SDF Configuration File . . . . . . . . . . . . . . . . . . . . . . . . .

3-22Compiling and Elaborating Your DesignYou can also enter the following runtime options on the vcs command line or in the file that you specify with

C-48Compile-Time OptionsOptions for Cell Definition+nolibcellDoes not define as a cell modules defined in libraries unless they are under the `celldef

C-49Compile-Time OptionsAs an alternative to using the +nocelldefinepli+1 option, you can add an entry in the virsims.tab AND virsims_pp.tab files (lo

C-50Compile-Time Optionshost ID of your work station (used in licensing), the version of the VCS compiler (same as VCS) and the VCS build date.Options

C-51Compile-Time Options-cTells VCS to compile the source files, generate the intermediate C, assembly, or object files, and compile or assemble the C

C-52Compile-Time Optionsarguments:%vcs top.v test.c -CFLAGS "-I$VCS_HOME/include"or%setenv CWD ‘pwd‘%vcs top.v test.c -CFLAGS "-I$CWD/i

C-53Compile-Time Optionsplatforms), generating intermediate assembly files (-gen_asm) and then their parallel assembly, or generating intermediate C f

C-54Compile-Time OptionsOptions for Source Protection+autoprotect[file_suffix]Creates a protected source file; all modules are encrypted. +auto2protec

C-55Compile-Time Optionssingle file. Output is saved in tokens.v file. You can substitute -Xman for -Xmangle. The argument number can be 1, 4, 12, or

C-56Compile-Time OptionsOptions for Mixed Analog/Digital Simulation+ad=partition_filenameSpecifies the partition file that you use in mixed Analog/Dig

C-57Compile-Time Options-parameters filenameChanges parameters specified in the file to values specified in the file. The syntax for a line in the fil

3-23Compiling and Elaborating Your DesignSeveral runtime options, such as -cm, -cm_dir, -cm_name, +notimingcheck, and +no_tchk_msg, are also compile-t

C-58Compile-Time Optionssource files that do. Do not include spaces when specifying the arguments to this option.-override_timescale=time_unit/time_pr

C-59Compile-Time OptionsTetraMAX+tetramaxEnables simulation of TetraMAX’s testbench in zero delay mode.Make Accessing an Undeclared Bit an Error Condi

C-60Compile-Time OptionsMemories and Multi-Dimensional Arrays (MDAs)+memcbkEnables callbacks for memories and multi-dimensional arrays (MDAs). Use thi

C-61Compile-Time OptionsHardware Modeling-lmc-hmCompiles a design that instantiates a hardware model. Including this option is an alternative to speci

C-62Compile-Time OptionsSpecifying the Name of the Executable File-o nameSpecifies the name of the executable file. In UNIX the default is simv.Return

C-63Compile-Time Options

C-64Compile-Time Options

C-1Simulation OptionsCSimulation Options CThis appendix describes the options and syntax associated with the simv executable. These runtime options ar

C-2Simulation Options• Options for Specifying VERA Object Files• Options for Coverage Metrics• Options for Enabling and Disabling Specify Blocks• Opti

C-3Simulation Options+ntb_enable_solver_trace=valueEnables a debug mode that displays diagnostics when VCS executes a randomize() method call. Allowed

3-24Compiling and Elaborating Your DesignIf the csrc working directory is not located on a local disk, set the incremental compile directory so that i

C-4Simulation Options+ntb_solver_mode=valueAllows you to choose between one of two constraint solver modes. When set to 1, the solver spends more prep

C-5Simulation Options./simv.vdb/scov/results.db and ./simv.vdb/reports/ova.report files. Use this option if you want data and reports from a series of

C-6Simulation Options-ova_simend_max_fail NTerminates the simulation if the number of failures for any assertion reaches N. You must supply N, otherwi

C-7Simulation OptionsfilterBlocks reporting of trivial implication successes. These happen when an implication construct registers a success only beca

C-8Simulation OptionsnopostprocDisables the display of the SVA coverage summary at the end of simulation. This summary looks like this for each cover

C-9Simulation Options- A file name containing () results in a Badly placed ()’s message.- A file name containing ! results in an Event not found messa

C-10Simulation Optionstakes commands from the standard input. This option is normally used along with the -s runtime option and a +cli+number compile-

C-11Simulation OptionsfsmMonitors for FSM coverage.tglMonitors for toggle coverage.pathMonitors for path coverage.branchMonitors for branch coverageas

C-12Simulation Options-cm_name filenameAs a compile-time or runtime option, specifies the name of the intermediate data files. On the cmView command l

C-13Simulation OptionsIf you need the delayed versions of the signals in negative timing checks but want faster performance, include this option at ru

3-25Compiling and Elaborating Your DesignCompile-Time Options That Impede or Accelerate VCSThere are a number of compile-time options that enhance or

C-14Simulation OptionsOptions for Controlling Messages-qQuiet mode; suppresses display of VCS header and summary information. Suppresses the proprieta

C-15Simulation Options+vcs+nostdoutDisables all text output from VCS including messages and text from $monitor and $display and other system tasks. VC

C-16Simulation OptionsNote: VCS automatically increases the buffer size as needed to comply with this limit. +vpdfile+filenameSpecifies the name of

C-17Simulation Options+vpdignoreTells VCS to ignore any $vcdplusxx system tasks and license checking. By default, VCS checks out a VPD PLI license if

C-18Simulation OptionsOperations-grw filenameSets the name of the $gr_waves output file to the specified filename. The default file name is grw.dump.

C-19Simulation OptionsOptions for Specifying Min:Typ:Max Delays+maxdelaysSpecifies using the maximum delays in min:typ:max delay triplets in module pa

C-20Simulation Options+typdelaysSpecifies using the typical delays in min:typ:max delay triplets in module path delays and timing checks, if you compi

C-21Simulation Options+vcs+flush+logIncreases the frequency of dumping both the compilation and simulation log files.+vcs+flush+dumpIncreases the freq

C-22Simulation OptionsGeneral OptionsViewing the Compile-Time Options Used to Create the Executable-E programStarts the program that displays the comp

C-23Simulation OptionsSuppressing the $stop System Task+vcs+ignorestopTells VCS to ignore the $stop system tasks in your source code.Enabling User-Def

3-26Compiling and Elaborating Your Design+spl_readTreats output ports as inout ports.Compile-Time Options That Slow Down Compilation-gen_asm Generates

C-24Simulation OptionsIf during a simulation run, acc_handle_simulated_net is called before MIPD annotation happens, VCS issues a warning message. Whe

D-1Compiler Directives and System TasksDCompiler Directives and System Tasks DThis appendix describes: • Compiler Directives• System Tasks and Functio

D-2Compiler Directives and System TasksCompiler DirectivesCompiler directives are commands in the source code that specify how VCS compiles the source

D-3Compiler Directives and System TasksCompiler Directives for Setting Defaults`default_nettypeSets default net type for implicit nets. See IEEE Std 1

D-4Compiler Directives and System Tasks`endifUsed with `ifdef.. Specifies the end of a group of lines specified by the ‘ifdef or ‘else compiler direct

D-5Compiler Directives and System Tasks‘ifndefSpecifies compiling the source code that follows if the specified text macro is not defined. See IEEE St

D-6Compiler Directives and System Tasks`delay_mode_distributedIgnores the module path delays specified in specify blocks in modules under this compile

D-7Compiler Directives and System TasksCompiler Directives for Backannotating SDF Delay Values‘vcs_mipdexpandIf the +oldsdf compile-time option has be

D-8Compiler Directives and System Tasks`endprotectedDefines the end of protected code. Syntax:‘endprotected`protectDefines the start of code to be pro

D-9Compiler Directives and System TasksCompiler Directive for Setting the Time Scale`timescaleSets the timescale. See IEEE Std 1364-2001 page 357. Syn

3-27Compiling and Elaborating Your Design-O1Applies fewer optimizations when generating C code intermediate files and compiling them. Applying fewer o

D-10Compiler Directives and System TasksTo specify more than one search library enter additional dir or file keywords, for example:‘uselib dir = /net/

D-11Compiler Directives and System TasksSystem Tasks for SystemVerilog Assertions Severity$fatalGenerates a runtime fatal assertion error. See the Acc

D-12Compiler Directives and System TasksSystem Tasks for SystemVerilog Assertions$onehotReturns true if only one bit in the expression is true. See t

D-13Compiler Directives and System Tasks$dumponStarts recording value change information in the VCD file. See IEEE std 1364-2001 page 326.$dumpfileSpe

D-14Compiler Directives and System Tasks$fflushVCS stores VCD data in the operating system’s dump file buffer and as simulation progresses, reads from

D-15Compiler Directives and System TasksSystem Tasks for LSI Certification VCD and EVCD Files$lsi_dumpportsFor LSI certification of your design, this

D-16Compiler Directives and System Taskstasks both generated simulation history files for LSI certification and had identical syntax except for the na

D-17Compiler Directives and System Tasks$dumpportsallBy default VCS writes to files only when a signal changes value. The $dumpportsall system task r

D-18Compiler Directives and System Tasks$dumpportslimitSpecifies the maximum file size of the file specified by the $lsi_dumpports or $dumpports syste

D-19Compiler Directives and System TasksNote:To use the system tasks for VPD files you must compile your source code with the -I or -PP compile-time o

3-28Compiling and Elaborating Your Design% vcs -Mdir=csrc_debug -debug source.vThis command line enables debugging capabilities but also results in a

D-20Compiler Directives and System Tasks$vcdplusdeltacycleonEnables delta cycle recording in the VPD file for post-processing. Syntax:$vcdplusevent(ne

D-21Compiler Directives and System Tasks$vcdplusdumpportsonRecords transition times and values of ports in a module instance. A level value of 0 tells

D-22Compiler Directives and System Tasks$vcdplusflushTells VCS to “flush” or write all the simulation results in memory to the VPD file at the time VC

D-23Compiler Directives and System Tasksdim2LsbThis is an optional argument with the same functionality as dim1Lsb, but refers to the second dimension

D-24Compiler Directives and System Tasks$vcdplusmemorydumpRecords (dumps) a snapshot of the values in a memory or multi-dimensional array into the VPD

D-25Compiler Directives and System Taskslevel_number Specifies the number of hierarchy scope levels for which to record signal value changes (a zero v

D-26Compiler Directives and System Tasks$assert_monitor([0|1,]assertion_identifier...);Where:0Specifies reporting on the assertion if it is active (VC

D-27Compiler Directives and System TasksCommands$systemExecutes operating system commands. Syntax:$system("command");Code example:$system(&q

D-28Compiler Directives and System Tasks$nologDisables writing to the vcs.log file or the log file specified by either the -l runtime option or the $l

D-29Compiler Directives and System Tasks$monitoroffDisables the $monitor system task. See IEEE std 1364-2001 page 286.$monitoronRe-enables the $monito

3-29Compiling and Elaborating Your DesignNote:• 64-bit machines have more capacity than 32-bit machines, but there is a performance trade-off.• The pr

D-30Compiler Directives and System Tasks$fgetsReads a string from a file. See IEEE Std 1364-2001 page 290.$fmonitor[b|h|0]Writes to a file when an arg

D-31Compiler Directives and System Tasks$sformatAssigns a string value to a specified signal. See IEEE Std 1364-2001 pages 289-290.$sscanfReads charac

D-32Compiler Directives and System Tasks$writemembWrites binary data in a memory to a file. Syntax:$writememb ("filename",memory [,start_add

D-33Compiler Directives and System Tasks$finishEnds simulation.See IEEE std 1364-2001 page 301.System Tasks for Timing Checks$disable_warningsDisables

D-34Compiler Directives and System Tasks$enable_warnings("timing"[,module_instance,...]);If you specify a module instance, this system task

D-35Compiler Directives and System Tasks$recremReports a timing violation if a data event occurs less than a specified time limit before or after a re

D-36Compiler Directives and System Tasks$setupholdCombines the $setup and $hold system tasks.See IEEE Std 1364-1995 page 189 for the official descript

D-37Compiler Directives and System Tasks$q_examProvides statistical information about activity at the queue.See IEEE Std 1364-2001 page 307.$q_fullRet

D-38Compiler Directives and System TasksSystem Tasks for Probabilistic Distribution$dist_exponentialReturns random numbers where the distribution func

D-39Compiler Directives and System Tasks$reset_countKeeps track of the number of times VCS executes the $reset system task in a simulation session. Se

3-30Compiling and Elaborating Your DesignError: malloc(400) returned 0: Not enough spaceerror: out of virtual memory (swap space)error: calloc(16384,

D-40Compiler Directives and System TasksCounting the Drivers on a Net$countdriversCounts the number of drivers on a net.See IEEE std 1364-2001 page 73

D-41Compiler Directives and System TasksSaving and Restarting The Simulation State$saveSaves the current simulation state in a file.See IEEE std 1364-

D-42Compiler Directives and System Tasks$xzcheckoffSuppress the warning message every time VCS evaluates a conditional expression to have an X or Z va

E-1PLI Access RoutinesEPLI Access Routines EVCS comes with a number of access routines. The following access routines are described in this appendix:•

E-2PLI Access Routines• Access Routine for Signal in a Generate Block• VCS API RoutinesAccess Routines for Reading and Writing to MemoriesVCS comes wi

E-3PLI Access Routinesacc_setmem_bitstrWrites a string of binary bits (including x and z) to a Verilog memory word. See "acc_setmem_bitstr"

E-4PLI Access Routinesacc_setmem_intYou use the acc_setmem_int access routine to write an integer value to specific bits in a Verilog memory word.acc_

E-5PLI Access Routinesacc_getmem_intYou use the acc_getmem_int access routine to return an integer value for certain bits in a Verilog memory word.acc

E-6PLI Access Routinesacc_clearmem_intYou use the acc_clearmem_int access routine to write zeros to all bits in a memory.Examples The following code e

E-7PLI Access Routines• Example D-3 shows the Verilog source code containing these system tasks.Example D-1 C Source Code for Functions Calling acc_ge

3-31Compiling and Elaborating Your Design• Avoid using debug options like -debug, -debug_all... switches.• In the pli.tab files, beware of ACC calls

E-8PLI Access Routines memhand = acc_handle_tfarg(1); if(!memhand) error_handle("NULL MEM HANDLE\n"); row = acc_fetch_tfarg_int(2

E-9PLI Access RoutinesThe function with the clear_mem identifier likewise calls the acc_fetch_tfarg_int routine to get a handle and then calls acc_cle

E-10PLI Access Routines // print values through acc_getmem_int #1 len = bfinish - bstart + 1; $display(); $display("Begin Memory Values");

E-11PLI Access Routinesacc_setmem_hexstrYou use the acc_setmem_hexstr access routine for writing the corresponding binary representation of a hexadeci

E-12PLI Access RoutinesExamplesThe following code examples illustrates the use of acc_setmem_hexstr:• Example D-4 shows the C source code for an appli

E-13PLI Access RoutinesExample D-4 shows the source code for a PLI application that: 1. Reads a data file named initfile to find the memory identifier

E-14PLI Access Routines testbench.U1.slave_addr[0], testbench.U1.slave_addr[1], testbench.U1.slave_addr[2], testbench.U1.load, te

E-15PLI Access Routinesacc_getmem_hexstrYou use the acc_getmem_hexstr access routine to get a hexadecimal string from a Verilog memory.acc_getmem_hexs

E-16PLI Access Routinesacc_setmem_bitstrYou use the acc_setmem_bitstr access routine for writing a string of binary bits (including x and z) to a Veri

E-17PLI Access Routinesacc_getmem_bitstrYou use the acc_getmem_bitstr access routine to get a bit string, including x and z values, from a Verilog mem

xiiNegative Timing Checks for XYZ. . . . . . . . . . . . . . . . . . . . . . 14-2The $setuphold Timing Check Extended Syntax . . . . . . . . . . 14-7N

3-32Compiling and Elaborating Your DesignSetting up the Compiler and LinkerBefore running the 64-32-bit cross-compilation, Synopsys recommends that yo

E-18PLI Access Routinesacc_handle_mem_by_fullnameReturns a handle to a memory that can only be used as a parameter to acc_readmem.acc_handle_mem_by_fu

E-19PLI Access Routinesacc_readmemYou use the acc_readmem access routine to read a data file into a memory. It is similar to the $readmemb or $readmem

E-20PLI Access RoutinesExamplesThe following code examples illustrate the use of acc_readmem and acc_handle_mem_by_fullname.Example D-8 C Source Code

E-21PLI Access Routinesacc_getmem_rangeYou use the acc_getmem_range access routine to access the upper and lower limits of a memory.acc_getmem_rangeSy

E-22PLI Access Routinesacc_getmem_sizeYou use the acc_getmem_size access routine to access the number of elements in a memory.acc_getmem_sizeSynopsis:

E-23PLI Access Routinesacc_getmem_word_intYou use the acc_getmem_word_int access routine to access the integer value of an element (or word, address,

E-24PLI Access Routinesacc_getmem_word_rangeYou use the acc_getmem_word_range access routine to access the least significant bit of an element (or wor

E-25PLI Access RoutinesAccess Routines for Multidimensional ArraysThe type for multidimensional arrays is defined in the vcs_acc_user.h file. Its name

E-26PLI Access Routinestf_mdanodeinfo and tf_imdanodeinfoYou use these routines to access parameter node information from a multidimensional array.Str

E-27PLI Access Routines int node_vec_size; int node_sign; int node_ms_index; int node_ls_index; int node_mem_size; int *

3-33Compiling and Elaborating Your DesignNote that these are only experimental values and you may need to further adjust them to fit your particular s

E-28PLI Access Routinesacc_get_mda_rangeThe acc_get_mda_range routine returns the ranges of a multidimensional array.If you have a multidimensional ar

E-29PLI Access RoutinesAnd you call a routine, such as the following:handle hN = acc_handle_by_name(my_mem);acc_get_mda_range(hN, &size, &msb,

E-30PLI Access RoutinesIf you have a multidimensional array such as the following:reg [7:0] my_mem[255:0][255:0][31:0];And you call a routine, such as

E-31PLI Access Routinesacc_getmda_bitstr()You use the acc_getmda_bitstr access routine to read a bit string, including x and z values, from a multidim

E-32PLI Access RoutinesIt yields the following string from my_mem[5][5][10][3:5].acc_setmda_bitstr()You use the acc_setmda_bitstr access routine to wr

E-33PLI Access Routineshandle hN = acc_handle_by_name(my_mem);acc_setmda_bitstr(hN, &bitStr, dim, 3, 3);It writes 111 in my_mem[5][5][10][3:5].Acc

E-34PLI Access Routinesvcs_dist_poissonReturns random numbers with a specified mean. See "vcs_random" on page E-34 for details.These routine

E-35PLI Access Routinesvcs_random_const_seedYou use this routine to return a random number and you supply an integer constant argument as the seed for

E-36PLI Access Routinesvcs_dist_uniformYou use this routine to return a random number uniformly distributed between parameters.vcs_dist_uniformSynopsi

E-37PLI Access Routinesvcs_dist_normalYou use this routine to return a random number with a specified mean and standard deviation.vcs_dist_normalSynop

3-34Compiling and Elaborating Your DesignRunning a 64-Bit Compilation and SimulationIf you are encountering memory issues at runtime, you can use the

E-38PLI Access Routinesvcs_dist_exponentialYou use this routine to return a random number where the distribution function is exponential.vcs_dist_expo

E-39PLI Access Routinesvcs_dist_poissonYou use this routine to return a random number with a specified mean.Access Routines for Returning a String Poi

E-40PLI Access RoutinesFor your convenience VCS provides the acc_fetch_paramval_str routine to directly return a string pointer.acc_fetch_paramval_str

E-41PLI Access Routinesacc_lsi_dumpports_closeCloses specified VCDE files. See "acc_lsi_dumpports_close" on page E-45 for details.acc_lsi_du

E-42PLI Access Routinesacc_lsi_dumpports_allSyntaxint acc_lsi_dumpports_all(char *filename)SynopsisAdds a checkpoint to the file. This is a PLI interf

E-43PLI Access Routines acc_lsi_dumpports_all(outfile); acc_lsi_dumpports_flush(outfile);} ... if (resume_dumping_now) acc_lsi_dump

E-44PLI Access RoutinesExample D-12 Example of acc_lsi_dumpports_all#include "acc_user.h"#include "vcs_acc_user.h" handle inst

E-45PLI Access Routinesacc_lsi_dumpports_closeSyntaxint acc_lsi_dumpports_call(handle instance, char *filename)SynopsisCloses specified VCDE files. Th

E-46PLI Access RoutinesCautionA call to this function can also close files opened by the $lsi_dumpports or $dumpports system tasks.acc_lsi_dumpports_f

E-47PLI Access Routines /* add checkpoint (no need to enable dumping) */ acc_lsi_dumpports_all(outfile); acc_lsi_dumpports_flush(outfile);}...

3-35Compiling and Elaborating Your DesignCompiling With Radiant TechnologyYou specify Radiant Technology optimizations at compile time. Radiant Techno

E-48PLI Access Routinesif (time == yada_yada) acc_lsi_dumpports_off(outfile);... if (time == yada_yada_yada) { /* add checkpoint (no need t

E-49PLI Access RoutinesExample D-16 Example or acc_lsi_dumpports_misc#include "acc_user.h"#include "vcs_acc_user.h" void my_ta

E-50PLI Access Routinesif (time == yada_yada) acc_lsi_dumpports_off(outfile);... if (time == yada_yada_yada) { /* add checkpoint (no need to

E-51PLI Access Routineschar *outfile = "device.evcd"; /* use IEEE format for this file */acc_lsi_dumpports_setformat(USE_DUMPPORTS_FORMA

E-52PLI Access Routinesacc_lsi_dumpports_setformatSyntaxint acc_lsi_dumpports_setformat(lsi_dumpports_format_type format)Where the valid lsi_dumports_

E-53PLI Access Routinesacc_lsi_dumpports_setformat(USE_DUMPPORTS_FORMAT_LSI);if (acc_lsi_dumpports_call(instance, outfile2)) { /* error */}...Cauti

E-54PLI Access Routineschar *outfile1 = "device.evcd1";char *outfile2 = "device.evcd2"; /* Include VHDL drivers in this report

E-55PLI Access Routinesacc_mod_lcb_fetchReturns an array of breakable lines. See "acc_mod_lcb_fetch" on page E-59 for details.acc_mod_lcb_fe

E-56PLI Access RoutinesReturnsNo return value.Example D-21 Example of acc_mod_lcb_add#include <stdio.h>#include "acc_user.h"#include &

E-57PLI Access Routinesacc_mod_lcb_delSyntaxvoid acc_mod_lcb_del(handle handleModule, void (*consumer)(), char *user_data)SynopsisUnregisters a line c

3-36Compiling and Elaborating Your DesignThe only SystemVerilog constructs that work with Radiant Technology are SystemVerilog assertions that refer t

E-58PLI Access Routines acc_fetch_fullname (parent_mod)); acc_mod_lcb_del (parent_mod, line_call_back, parent_mod); while ((

E-59PLI Access RoutinesExample D-23 Example of acc_mod_lcb_enabledif (! acc_mod_lcb_enable) { tf_warning("Line callbacks not enabled. Please r

E-60PLI Access RoutinesExample D-24 Example of acc_mod_lcb_fetch#include <stdio.h>#include "acc_user.h"#include "vcs_acc_user.h&q

E-61PLI Access RoutinesThe tag field is a unique identifier used to distinguish ‘include files. For example, in the following Verilog module, the brea

E-62PLI Access Routines if ((plocation = acc_mod_lcb_fetch2(handleModule)) != NULL) { int i; io_printf("%s:\n", acc_fet

E-63PLI Access RoutinesReturns NULL if the module is source protected.Example D-26 Example of acc_mod_sfi_fetch#include <stdio.h>#include "

E-64PLI Access RoutinesAccess Routines for Source ProtectionThe enclib.o file provides a set of access routines that you can use to create application

E-65PLI Access RoutinesvcsSpEncodingThis routine gets the current state of encoding. See "vcsSpEncoding" on page E-71 for details.vcsSpGetFi

E-66PLI Access RoutinesvcsSpSetPliProtectionFlagSets the PLI protection flag. See "vcsSpSetPliProtectionFlag" on page E-80 for details.vcsSp

E-67PLI Access Routines write_error += vcsSpWriteString(esp, "This text will *not* be encrypted.\n"); writ

3-37Compiling and Elaborating Your DesignYou specify the configuration file with the +optconfigfile compile-time option. For example:+optconfigfile+fi

E-68PLI Access RoutinesvcsSpCloseSyntaxvoid vcsSpClose(vcsSpStateID esp)SynopsisThis routine frees the memory allocated by vcsSpInitialize(). Call it

E-69PLI Access RoutinesReturnsNon-zero if there was an error writing to the output file, 0 if successful.Example D-29 Example of vcsSpEncodeOffvcsSpSt

E-70PLI Access RoutinesSynopsisThis function performs two operations:1. It inserts a header section which contains the ‘protected compiler directive i

E-71PLI Access RoutinesCautionYou must call vcsSpInitialize() and vcsSpSetFilePtr() before calling this routine.vcsSpEncodingSyntaxint vcsSpEncoding(v

E-72PLI Access RoutinesvcsSpGetFilePtrSyntaxFILE *vcsSpGetFilePtr(vcsSpStateID esp)SynopsisThis routine just returns the value previously passed to th

E-73PLI Access RoutinesvcsSpInitializeSyntaxvcsSpStateID vcsSpInitialize(void)SynopsisThis routine allocates a source protect object.Returns a handle

E-74PLI Access RoutinesCautionThis routine must be called before any other source protection routine. A NULL return value means the call to malloc() f

E-75PLI Access Routines ... } if (!esp) break; /* done */ } /* next line should be ‘endprotected_ip */ fgets(linebu

E-76PLI Access Routines if (vcsSpWriteString(esp, "This text will NOT be encrypted.\n")) ++write_error; if (vcsSpEncodeOn(esp)) +

E-77PLI Access RoutinesExample D-36 Example of vcsSpOvaEnable#include "enclib.h"#include "encint.h" int write_error = 0;vcsSp

3-38Compiling and Elaborating Your DesignHere:moduleKeyword that specifies that the attributes in this statement apply to all instances of the modules

E-78PLI Access RoutinesvcsSpSetDisplayMsgFlagSyntaxvoid vcsSpSetDisplayMsgFlag(vcsSpStateID esp, int enable)SynopsisThis routine sets the DisplayMsg f

E-79PLI Access RoutinesExample D-38 Example of vcsSpSetFilePtrvcsSpStateID esp = vcsSpInitialize();FILE *fp = fopen("protected.file", "

E-80PLI Access RoutinesvcsSpEncodeOn(esp); /* start protected region */vcsSpWriteString(esp, "this text will be encrypted and lic

E-81PLI Access RoutinesThis routine only affects encrypted Verilog files. Encrypted SDF files, for example, are not affected.ReturnsNo return value.Ex

E-82PLI Access RoutinesReturnsNon-zero if the file pointer has not been set (see "vcsSpSetFilePtr" on page E-78) or if there was an error wr

E-83PLI Access RoutinesvcsSpWriteStringSyntaxint vcsSpWriteString(vcsSpStateID esp, char *s)SynopsisThis routine writes a character string to the prot

E-84PLI Access Routinesencrypted.\n")) ++write_error; if (vcsSpEncodeOff(esp)) ++write_error;if (vcsSpWriteString(esp, "This text wil

E-85PLI Access RoutinesVCS API RoutinesTypically VCS controls the PLI application. If you write your application so that it controls VCS you need thes

E-86PLI Access RoutinesIf t is less than the current simulation time, VCS returns control to the calling routine.

IN-1IndexSymbols-a filename 4-13, C-13-ams_discipline B-56-ams_iereport B-56-as assembler B-50-ASFLAGS B-50-assert 20-21, 20-23, 23-36, B-31-B B-62-C

3-39Compiling and Elaborating Your DesigntreeKeyword that specifies that the attributes in this statement apply to all instances of the modules in the

IN-2-k 9-13, C-10, C-15-l C-15-l filename 1-15, 1-19, 4-13, B-60, C-13-ld linker B-50-LDFLAGS B-50-line 1-15, B-17-lmc-hm B-61-lmc-swift 16-16, B-45-l

IN-3-Xnoman B-55-Xnomangle B-55-y 1-17, B-4"A" specifier of abstract access 18-7"C" specifier of direct access 18-7$ token 23-5$as

IN-4$period D-34$printtimescale D-32$q_add D-36$q_exam D-37$q_full D-37$q_initialize D-37$q_remove D-37$random 2-33, D-38$readmemb D-31$readmemh D-31$

IN-5+csdf+precompile 13-7, B-35+define+macro=value 1-15, B-61+delay_mode_distributed 12-21, B-33+delay_mode_path 12-21, B-32+delay_mode_unit 12-22, B-

IN-6+sdfverbose C-14+spl_read B-59+systemverilogext B-15+timopt 13-40+transport_int_delays 12-7, 12-10, 12-12, B-34+transport_path_delays 12-7, 12-9,

IN-7‘noportcoerce 2-15, D-8‘nounconnected_drive D-10‘portcoerce D-8‘protect D-8‘protected D-8‘race D-5‘resetall D-3‘timescale D-9‘unconnected_drive D-

IN-8$assert_monitor 23-64, D-25$assert_monitor_off 23-64, D-26$assert_monitor_on 23-64, D-26assertion classes 21-63Assertion failure, displaying messa

IN-9char**direct access for C/C++ functionsformal parameter type 18-20+charge_decay B-32check 21-32check argument to -ntb_opts B-12check PLI specifica

IN-10triggering 3-4verbose messages B-46compiling, design, design, testbench and Verilog module 21-27compiling, design, shell, and Verilog module 21-2

IN-11$deposit D-40design, compiling 21-27DEVICE SDF construct 13-28direct access for C/C++ functionsexamples 18-22–18-27formal parameterstypes 18-20ru

3-40Compiling and Elaborating Your DesignConfiguration File Statement ExamplesThe following are examples of statements in a configuration file.module

IN-12extends directiveadvice 24-131introduction 24-131extern declaration 18-7extern declarations 18-27F-fsyntax 21-30-F filename B-38-f filename 1-15,

IN-13Ignoring Calls and License Checking 6-27, C-17implications 23-19implicit .* connections 22-58implicit .name connections 22-58+incdir 1-15, B-5‘in

IN-14linking by hand B-51passing options to the linker B-50specifying another linker B-50+lint B-46Lint, using 3-10–3-12linter rules, OVA code checkin

IN-15+multisource_int_delays 12-6, 13-13, B-33, B-34-Mupdate B-6Nnative code generatingspecifying B-62Native Testbenchin VCS 9-13+nbaopt B-33-nbt_v1 2

IN-16object data members 9-9+old_ntc B-43+oldsdf 13-5, B-36OpenVera Assertionsbenefits 20-2flow 20-7introduction 20-2overview 20-4operating system com

IN-17-override_timescale B-58P-P pli.tab 17-20, B-41packed arrays 22-14packed keyword 22-11packed structure 22-11parallel compilation B-8, B-52paralle

IN-18prx ACC capability 17-14public 24-63+pulse_e/number 12-8, 12-9, 12-12, 12-17, 12-18, B-40+pulse_int_e 12-7, 12-8, 12-10, 12-12, B-40+pulse_int_r

IN-19passing a value from before to after a reset D-39resetting VCS to simulation time 0 D-38$restart D-41results 20-41, 20-42return range of a C/C++

IN-20simv executable file 1-13size PLI specification 17-9$skew D-36slicing arrays 22-16SmartQreverse() 24-165, 24-166solve-beforehard 24-92Source Pane

IN-21setting 5-9$timeformat D-32-timescale B-57‘timescale D-9timing check system tasksdisablingin specific module instances 13-40timing check system t

3-41Compiling and Elaborating Your Designinstance {mod1.mod2_inst1.mod3_inst1, mod1.mod2_inst1.rega} {noOpt};In this example, the module statement dis

IN-22vc_FillWithScalar() 18-72vc_get2stMemoryVector() 18-67vc_get2stVector() 18-55vc_get4stMemoryVector() 18-64vc_get4stVector() 18-54vc_getInteger()

IN-23vcdpost utility 7-2syntax 7-4VCSpredefined text macro D-4using Native Testbench 9-13-vcs 21-10vcs command line 1-13+vcs+boundscheck 3-20, B-59+vc

IN-24syntax 24-88void*direct access for C/C++ functionsformal parameter type 18-20void**direct access for C/C++ functionsformal parameter type 18-20VP

xiiiUsing LMTV SmartModel Window Commands . . . . . . . . . . . . . . 16-10Entering Commands Using the SWIFT Command Channel . . . . 16-13Using the CL

3-42Compiling and Elaborating Your Designfirst tree statement exampletree {mod1,mod2} {Opt};This example is for a design with the following module hie

3-43Compiling and Elaborating Your Designdown the hierarchy than the instances of the specified modules, mod1 and mod2.A tree statement with a depth o

3-44Compiling and Elaborating Your Designcounting up from there. (Leaf level module instances contain no module instantiation statements.) In this exa

3-45Compiling and Elaborating Your DesignLibrary Mapping Files and ConfigurationsLibrary mapping and configurations are an LCA (Limited customer Avail

3-46Compiling and Elaborating Your DesignThe following is an example of the contents of a library mapping file:library lib1 /net/design1/design1_1/*.v

3-47Compiling and Elaborating Your DesignVCS assigns the source file dev.v to the default logical library called work.You can specify either absolute

3-48Compiling and Elaborating Your DesignResolving ‘include Compiler DirectivesThe source file in a logical library might include the ‘include compile

3-49Compiling and Elaborating Your Design• Specifies overrides to the logical library search order for all instances of specified cellsYou can define

3-50Compiling and Elaborating Your DesignendconfigIs the keyword that ends a configuration.The default ClauseThe default clause specifies the logical

3-51Compiling and Elaborating Your DesignuseSpecifies that the instance is an instance of the specified cell in the specified logical library.The foll

xivSupport for the vpi_register_systf Routine. . . . . . . . . . . . . . . 17-31PLI Table File for VPI Routines . . . . . . . . . . . . . . . . . . .

3-52Compiling and Elaborating Your Designparticular instances in a subhierarchy, then you can define a configuration for a higher level of the design.

3-53Compiling and Elaborating Your DesignThe -top compile-time option requires the +v2k or -sverilog compile-time option and the -new_dr compile-time

3-54Compiling and Elaborating Your Design

4-1Simulating Your Design4Simulating Your Design 1You can simulate your design with VCS using several options and techniques, which allow you to focus

4-2Simulating Your DesignRunning and Controlling a SimulationThis section describes how to simulate your design using the binary executable generated

4-3Simulating Your Design2. Choose Simulator > Setup, then start simulation from the Simulation Setup dialog box.3. Browse to the simulation execut

4-4Simulating Your DesignSave and RestartVCS provides a save and restart feature that allows checkpoints of the simulation to be saved at arbitrary ti

4-5Simulating Your DesignExample 4-1 Save and Restart Example% cat test.vmodule simple_restart;initial begin#10$display("one");$save("t

4-6Simulating Your DesignfourSave and Restart File I/OVCS remembers the files you opened via $fopen and reopens them when you restart the simulation.

4-7Simulating Your DesignFor example, if you load a memory image with $loadmemb at the beginning of the simulation and want to be able to restart from

xvint vc_is4stVector(vc_handle). . . . . . . . . . . . . . . . . . . . . . 18-37int vc_is2stVector(vc_handle). . . . . . . . . . . . . . . . . . . . .

4-8Simulating Your DesignRestarting at the CLI PromptThe $restart system task allows you to restart the simulation at the CLI prompt. Enter it with th

4-9Simulating Your DesignThis difference is the first argument.You can let VCS do some of this work for you by using the following source code:module

4-10Simulating Your DesignPassing Values From the Runtime Command LineThe $value$plusargs system function can pass a value to a signal from the simv r

4-11Simulating Your DesignHow VCS Prevents Time 0 Race ConditionsAt simulation time 0, VCS always executes the always blocks in which any of the signa

4-12Simulating Your DesignWith other Verilog simulators there are two possibilities at time 0:• The simulator executes the initial block first, initia

4-13Simulating Your DesignRuntime options that specify writing to a file slow down simulation. These runtime options are as follows:-a filenameAppends

4-14Simulating Your DesignFor memory usage it reports the following:• The amount of memory and the percentage of memory used by the VCS kernel, the de

4-15Simulating Your DesignThe Top Level ViewThis view shows you how much CPU time was used by: • Any PLI application that executes along with VCS • VC

4-16Simulating Your DesignIf there was CPU time used by a PLI application, you could use a tool such as gprof or Quantify to profile the PLI applicati

4-17Simulating Your Design• There are 10,000 instances of module FD2. The number of instances is a way to assess the CPU times used by these instances

xviint vc_getMemoryInteger(vc_handle, U indx). . . . . . . . . . 18-62void vc_putMemoryInteger(vc_handle, U indx, int) . . . . . 18-64void vc_get4stM

4-18Simulating Your Design• combinational logic including gates or built-in primitives and continuous assignment statements• user-defined tasks• user-

4-19Simulating Your DesignExample 4-5 Module to Construct Mapping View===========================================================================

4-20Simulating Your Design• An always block in this module definition used 27.44% of the TOTAL CPU time. Of all the CPU time consumed by all instances

4-21Simulating Your DesignThe Instance ViewThis view shows you the module instances that use the most CPU time. An instance must use more than 0.5% of

4-22Simulating Your DesignThe Program to Construct Mapping ViewThe program to construct mapping view lists the testbench constructs that use the most

4-23Simulating Your DesignExample 4-8 Top Level Construct View==============================================================================

4-24Simulating Your DesignExample 4-9 Top Level Construct View===========================================================================

4-25Simulating Your Design• Top Level View• Module View• The Program ViewThe Top Level ViewThis view shows you how much memory was used by: • Any PLI

4-26Simulating Your DesignIn this example there is no DPI or PLI application and VCS does not write a VCD or VPD file. VCS used 1163834 bytes of mem

4-27Simulating Your DesignThe Program ViewThe program view shows the amount of memory used, and the percentage of memory used, by each testbench progr

xviiVerilog Design Containing SystemC Leaf Modules. . . . . . . . . . . 19-6Input Files Required. . . . . . . . . . . . . . . . . . . . . . . . . . .

4-28Simulating Your Design

5-1Using the Discovery Visual Environment5Using the Discovery Visual Environment 2This chapter introduces the Discovery Visual Environment (DVE) graph

5-2Using the Discovery Visual EnvironmentOverview of DVE Window ConfigurationDVE has a completely flexible window model. This model is based on the co

5-3Using the Discovery Visual EnvironmentFigure 5-1 DVE TopLevel Frame Initial ViewMenu BarToolbarHierarchy BrowserSource WindowConsole TabsConsoleTcl

5-4Using the Discovery Visual EnvironmentDVE PanesA TopLevel window can contain any number of panes. A pane is a window that serves a specific debug p

5-5Using the Discovery Visual EnvironmentFigure 5-2 Window targeting icons Target icons can have the following two states:• Targeted – Icon has a dart

5-6Using the Discovery Visual Environment2. Click a corresponding window icon in the toolbar to open a window of that type. It will not be attached t

5-7Using the Discovery Visual EnvironmentDark blue color of dock handle (dock handle is the train track that connects to the X icon) indicates that th

5-8Using the Discovery Visual Environment• Select View>Go To Time, then enter a value in the Go To Time dialog box, and click Apply or OK.• Enter a

5-9Using the Discovery Visual EnvironmentFigure 5-3 Methods for Setting the Simulation Time Select View>Go To Time, enter a value in the Go To Time

iiCopyright Notice and Proprietary InformationCopyright © 2008 Synopsys, Inc. All rights reserved. This software and documentation contain confidentia

xviiiTransaction Level Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-31Interface Definition File . . . . . . . . . . . . . .

5-10Using the Discovery Visual EnvironmentSetting Display PreferencesYou can set preferences to customize the display of DVE windows and panes.To cus

5-11Using the Discovery Visual EnvironmentSelect whether to display the exit dialog box when closing DVE.- Debug Settings – Select signal compare para

5-12Using the Discovery Visual Environment- Hierarchy Browser – Set the appearance and initial filter states..- Data Pane – Set the appearance paramet

5-13Using the Discovery Visual Environment- Source window – Specify data and annotation loading options, line wrap, line number display, tab width, de

5-14Using the Discovery Visual Environment- Schematic window – Set line colors for schematic objects in Schematic and Path Schematic windows..- Select

5-15Using the Discovery Visual Environment- Waveform window – Set appearance parameters, signal levels to display, and marker value display settings..

5-16Using the Discovery Visual Environment- Coverage Settings – Set weights for display of line, condition, toggle, FSM, and cover metrics..- Coverage

5-17Using the Discovery Visual Environment3. Click OK to save your selections and close the dialog box, Save to save your settings and keep the dialog

5-18Using the Discovery Visual Environment

6-1VPD and EVCD File Generation6VPD and EVCD File Generation 1VPD and EVCD files contain simulation history data. In Verilog simulation, $vcdplus syst

xixOpenVera Assertions Post-Processing . . . . . . . . . . . . . . . . . . . . 20-24OVAPP Flow . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-2VPD and EVCD File Generation• System Tasks and Functions• Runtime Options• VPD Methodology• EVCD File GenerationAdvantages of VPDVPD offers the fol

6-3VPD and EVCD File GenerationSystem Tasks and Functions VPD system tasks capture and save value change data in a binary format so that you can view

6-4VPD and EVCD File Generationscope Specifies the name of the scope in which to record signal value changes (default is all).signalSpecifies the name

6-5VPD and EVCD File GenerationExample 2: Stop recording signal value changes for scope test.risc1.alu1.$vcdplusoff(test.risc1.alu1);Example 3: Stop r

6-6VPD and EVCD File Generation$vcdplusautoflushon When simulation stops, the $vcdplusautoflushon task automatically flushes to the VPD data file any

6-7VPD and EVCD File GenerationSystem Tasks and Functions for Multi-Dimensional ArraysThis section describes system tasks and functions that provide v

6-8VPD and EVCD File Generationdim1LsbName of the variable that contains the left bound of the first dimension. This is an optional argument. If there

6-9VPD and EVCD File GenerationNote that MDA system tasks can take 0 or more arguments, with the following caveats:• No arguments: The whole design is

6-10VPD and EVCD File GenerationIn order for VCS to provide memory data, it requires the +memcbk switch.VCS example: vcs -R -I mda.v +memcbkMemory de

6-11VPD and EVCD File GenerationFigure 6-1 Diagram of example: reg [7:0] mem01 [1:3] [4:6] [7:9][76543210][76543210] [76543210][76543210][76543210] [7

xxUse Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-63Enabling Verilog Parameter Expansion . . . . . . . . .

6-12VPD and EVCD File GenerationExample 6-2 $vcdplusmemon( mem01, addr1L );$vcdplusmemon( mem01 ); // Records all elements of mem01 to the VPD file

6-13VPD and EVCD File GenerationFigure 6-2 Diagram of example: $vcdplusmemon( mem01, addr1L );Example 6-3 $vcdplusmemon( mem01, addr1L, addr1R )addr1L

6-14VPD and EVCD File GenerationFigure 6-3 $vcdplusmemon( mem01, addr1L, addr1R );Example 6-4 $vcdplusmemon( mem01, addr1L, addr1R, addr2L );addr1L =

6-15VPD and EVCD File GenerationThe elements highlighted by the in the diagram in Figure 6-4 demonstrate Example 6-4.Figure 6-4 $vcdplusmemon( mem01

6-16VPD and EVCD File GenerationExample 6-5 $vcdplusmemon( mem01, addr1L, addr1R, addr2L, addr2R )addr1L = 2;addr1R = 2;addr2L = 5;addr2R = 6;$vcdplus

6-17VPD and EVCD File GenerationFigure 6-5 $vcdplusmemon( mem01, addr1L, addr1R, addr2L, addr2R );Example 6-6 Selected element: mem01[2][5][8]addr1L =

6-18VPD and EVCD File Generationaddr3L, addr3R );// Either command records element mem01[2][5][8]The element highlighted by the in the diagram in Fi

6-19VPD and EVCD File GenerationYou can specify only once the complete set of multi-dimensional array elements to be dumped. You can specify multiple

6-20VPD and EVCD File Generation2. For viewing in post simulation mode, enter the appropriate trace task at the VCS command line.3. For viewing in int

6-21VPD and EVCD File GenerationSource Statement System TasksNote: For VCS you must supply the -line option when creating the simulation executable.

xxiPreprocessor Directives . . . . . . . . . . . . . . . . . . . . . . . . . . 21-6Top Level Constructs . . . . . . . . . . . . . . . . . . . . . . .

6-22VPD and EVCD File GenerationHere:level The number of hierarchy scope levels to descend to stop recording line tracing (a zero value stops the reco

6-23VPD and EVCD File Generation$vcdplusdeltacycleoffThe $vcdplusdeltacycleoff task turns off reporting of delta cycle information starting at the nex

6-24VPD and EVCD File Generation$vcdplusglitchoff The $vcdplusglitchoff task turns off checking for zero delay glitches. Glitch detection is automatic

6-25VPD and EVCD File Generationevent_name A unique string which describes the event. This event name appears in the status bar of the Wave Window, Lo

6-26VPD and EVCD File GenerationSyntax: +vpdbufsize+nnHere nn is buffer size in megabytes. The minimum size is the size required to store two value ch

6-27VPD and EVCD File GenerationFile size is a direct result of circuit size, circuit activity, and the data being saved. Test cases show that VPD fil

6-28VPD and EVCD File GenerationThis option affects performance and memory usage for larger designs or longer runs. Syntax:+vpddrivers+vpdnoports to E

6-29VPD and EVCD File Generation+vpdnostrengths to Not Store Strength InformationBy default, VPD stores strength information on value changes to the V

6-30VPD and EVCD File GenerationConceptual Example of Using VPD System Tasks The example in Figure 6-7, shows the entry of the $vcdplus system tasks i

6-31VPD and EVCD File Generation• Create a task in source:task sigon_instreg;begin$vcdpluson(test.risc1.instreg);endendtaskThen call the task from sou

xxiiUsing Encrypted Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-44Testbench Functional Coverage . . . . . . . . . . . . . . .

6-32VPD and EVCD File GenerationVPD On/Off PLI RulesFollow these basic rules while using VPD On/Off PLI system tasks:• You can insert the $vcdpluson a

6-33VPD and EVCD File GenerationPerformance TipsThe following tips explain how to manage performance of VCS and VPD:• Normally you should save data fo

6-34VPD and EVCD File Generation• Saving statement execution for an entire design can increase simulation time by eight times or more. To limit perfor

6-35VPD and EVCD File GenerationEVCD File GenerationYou can create an EVCD file for the entire design in the following ways:• Using the runtime option

6-36VPD and EVCD File GenerationUsing System TasksYou can use $dumpports or $lsi_dumports system tasks to generate EVCD files. Using system tasks you

7-1VCD and VPD File Utilities7VCD and VPD File Utilities 1VCS comes with a number of utilities for processing VCD and VPD files. You can use these uti

7-2VCD and VPD File Utilities• The vcd2vpd Utility• The vpd2vcd Utility• The vpdmerge UtilityThe vcdpost UtilityYou use the vcdpost utility to generat

7-3VCD and VPD File Utilities$var wire 8 ! out1 [7:0] $endTherefore all the value changes and simulation times for signal out1 are for the entire sign

7-4VCD and VPD File UtilitiesSome back-end tools from other vendors fail when you input such a VCD file. You can use the vcdpost utility to create an

7-5VCD and VPD File UtilitiesThe vcdiff UtilityThe vcdiff utility compares two dump files and reports any differences it finds. The dump file can be o

xxiiiExample Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-71Running OpenVera Testbench with OVA . . . . . . . . . . . . . .

7-6VCD and VPD File UtilitiesThe vcdiff Utility SyntaxThe syntax of the vcdiff utility is as follows:vcdiff first_dump_file second_dump_file[-noabsent

7-7VCD and VPD File Utilities-allabsentsig Reports all absent signals. If this option is not present, by default, vcdiff reports only the first 10 abs

7-8VCD and VPD File Utilities-ignore [file] Removes any signals/scopes contained in the given file from value change diffing. The file contains a set

7-9VCD and VPD File Utilities-when expressionReports differences only when the given when expression is true. Initially this expression can consist on

7-10VCD and VPD File UtilitiesOptions for Filtering DifferencesThe following options filter out value change differences that are detected under certa

7-11VCD and VPD File Utilities-compare01xz (EVCD only) Converts all signal state information to equivalent 4-state values (0, 1, x, z) before differen

7-12VCD and VPD File Utilities-showmasters (VCD, EVCD files only) Shows collapsed net masters. VCS can split a collapsed net into several sub-nets whe

7-13VCD and VPD File UtilitiesThe vcat Utility SyntaxThe vcat utility has the following syntax:vcat VCD_filename [-deltaTime] [-raw] [-min time] [-max

7-14VCD and VPD File Utilities 10000 x 30 z-rawDisplays “raw” value changed data, organized by simulation time, rather than signal name.-min ti

7-15VCD and VPD File Utilities-spikesIndicates all zero-time transitions with the >> symbol in the left-most column. In addition, prints a summa

xxivTestbench Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-99NTB Performance Profiler . . . . . . . . . . . . . . .

7-16VCD and VPD File Utilities-vgenGenerates from a VCD file two types of source files for a module instance: one that models how the design applies s

7-17VCD and VPD File UtilitiesGenerating Source Files From VCD FilesThe vcat utility can generate Verilog source files that are one of the following:•

7-18VCD and VPD File UtilitiesThe name of the generated source file from testbench generation begins with testbench followed by the module and instanc

7-19VCD and VPD File UtilitiesThe following is an example of a configuration file:Example 7-1 Configuration Filetop.ad1testbench//moduleGenerationmodu

7-20VCD and VPD File Utilities#10 r1=1;#10 r2=1;#10 r1=0;#10 r2=0;#100 $finish;endpasser pa1 (int1,int2,r1,r2);adder ad1 (result,int1,int2);endmodulem

7-21VCD and VPD File UtilitiesNotice that the stimulus from the testbench module named test propagates through an instance of a module named passer be

7-22VCD and VPD File UtilitiesThis source file uses significantly less code to apply the same stimulus with the instance of module passer omitted.If w

7-23VCD and VPD File UtilitiesThe vcsplit UtilityThe vcsplit utility generates a VCD, EVCD, or VPD file that contains a selected subset of value chang

7-24VCD and VPD File UtilitiesThe include file must contain one scope or signal per line. Each presented scope/signal must be found in the input VCD,

7-25VCD and VPD File UtilitiesIf you specify an include_file and/or a selected_scope_or_signal, vcsplit includes all value changes of those signals/sc

xxvForce and Release on SystemVerilog Variables . . . . . . . . . . 22-20Automatic Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7-26VCD and VPD File UtilitiesLimitations • MDAs are not supported.• Bit/part selection for a variable is not supported. If this usage is detected,

7-27VCD and VPD File Utilities-mGive translation metrics during translation.-qSuppress printing of copyright and other informational messages.+deltacy

7-28VCD and VPD File UtilitiesModifies the string identifier for the Test-Fixture half of the spilt signal. Default is "TF".+indexlastAppend

7-29VCD and VPD File Utilities-qSuppress the copyright and other informational messages.-sAllow sign extension for vectors. Reduces the file size of t

7-30VCD and VPD File Utilities+dumpports+instanceGenerate an EVCD file for the specified module instance. If the path to the specified instance contai

7-31VCD and VPD File Utilities• All comments written after a command, must be preceded by a space.Example:dumpvars 1 adder4 //can write your comment

7-32VCD and VPD File Utilitiesdumpvcdports [level] instance [instance1 instance2 ...]Specify an instance whose port values are dumped to a VCD file.

7-33VCD and VPD File Utilitiesstarttime start_timeSpecify the start time to start dumping the value change data to the VCD file. If this command is no

7-34VCD and VPD File UtilitiesWave Window in Figure 7-1, there are three signal groups for the same signals in different VPD files.Figure 7-1 DVE Wave

7-35VCD and VPD File Utilities-qSpecifies quiet mode, disables the display of most output to the terminal.-hierSpecifies that you are merging VPD file

xxviThe $root Top-Level Global Declaration Space . . . . . . . . . . . 22-54New Data Types for Ports . . . . . . . . . . . . . . . . . . . . . . . .

7-36VCD and VPD File UtilitiesLimitationsThe verbose option -v may not display error or warning messages in the following scenarios:• If the reference

7-37VCD and VPD File Utilities

7-38VCD and VPD File Utilities

8-1Unified Command-Line Interface8Unified Command-Line Interface (UCLI) 2The Unified Command-Line Interface (UCLI) enables consistent interactive sim

8-2Unified Command-Line Interface• UCLI Interactive Commands• UCLI Command-Alias File• Operating System CommandsCompilation and Simulation Options for

8-3Unified Command-Line Interface-k keyFilenameRecords interactive commands used during a simulation to the file named KeyFilename, which can be used

8-4Unified Command-Line InterfaceUCLI Interactive CommandsThe following is a list of the UCLI interactive commands:Tool Invocation Commandsstart exe_n

8-5Unified Command-Line Interfacerun [-relative | -absolute time] [-posedge | -negedge | -change] [path_name]Advances simulation to a point specified

8-6Unified Command-Line Interfacecall [$cmd(...)]Calls a Verilog task.Tool Environment Array Commandssenv [element]Displays the environment array elem

8-7Unified Command-Line Interfacedrivers path_name [-full]Displays drivers of object path_name.loads path_name [-full]Displays load on object path_nam

xxviiConditions for Sequences . . . . . . . . . . . . . . . . . . . . . . . . 23-12Specifying That Sequence Match Within Another Sequence . . . . . .

8-8Unified Command-Line InterfaceHelper Routine Commandshelp -[full command]Displays information on all commands or specified command.alias [UCLI_comm

8-9Unified Command-Line InterfaceUCLI Command-Alias FileYou can call UCLI commands with aliases defined in a command-alias file. You can either create

8-10Unified Command-Line Interface

9-1Using the Old Command Line Interface (CLI)9Using the Old Command Line Interface (CLI) 1VCS provides the non-graphical debugger or CLI (Command Line

9-2Using the Old Command Line Interface (CLI)CLI CommandsYou can use basic Command Language Interface (CLI) commands to perform the following tasks:•

9-3Using the Old Command Line Interface (CLI)line Toggles line tracking.For example:cli> lineLine tracking is now ON.cli> lineLine tracking is n

9-4Using the Old Command Line Interface (CLI)upSteps out of current automatic task or function.For example:cli_65 > step upTime break at time 10020

9-5Using the Old Command Line Interface (CLI)loads nidDisplays the loads for the specified signal.For example:cli_23>show loads ramDataramData[7] (

9-6Using the Old Command Line Interface (CLI)show [allvariables|mailboxes|semaphores|threadsevent]allvariablesShows nets and registers in the current

9-7Using the Old Command Line Interface (CLI)mailboxes [m_id]Displays information about all mailboxes or the identified mailbox.semaphores [n_id]Displ

iContents1. Getting StartedWhat VCS Supports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3Main Components of VCS. . . . . .

xxviiiTcl Commands For SVA And OVA Functional Coverage Reports. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-49The assertCovReport Report

9-8Using the Old Command Line Interface (CLI)break -thread thread_idSets breakpoint in the specified thread.break at file:lineno/lineno -thread thread

9-9Using the Old Command Line Interface (CLI)Displaying Object Data Membersprint this In Vera code, prints the current object data members.For example

9-10Using the Old Command Line Interface (CLI)#1 in check_all at memsys0.vr:68#2 in memsys_test at memsys0.vr:19#3 in memsys_test_top.vshell upstackGo

9-11Using the Old Command Line Interface (CLI)Accessing Eventstrigger(0|1|2|3|4, event variable)Triggers an event in the testbench according to the fo

9-12Using the Old Command Line Interface (CLI)module top;reg a;reg [31:0] b;initial begina = 0;b = 32’b0;#10if (a) b = 32’b0;endendmodule% vcs +cli+2

9-13Using the Old Command Line Interface (CLI)Key FilesWhen you enter CLI commands (or commands in the DVE Interactive window), VCS by default records

9-14Using the Old Command Line Interface (CLI)Non-Graphical Debugging With the CLIIn order to use the CLI: • Enable it at compile time with the option

9-15Using the Old Command Line Interface (CLI)#include “port_bind.vr”#include “cpu.vr”program memsys_test{ // Start of memsys_test cpu cpu0 = new

9-16Using the Old Command Line Interface (CLI) fork {// fork process for CPU 0 repeat(256) { randflag = cpu0.randomize(); cpu0.

9-17Using the Old Command Line Interface (CLI)Use the following command line to run the simulation with debug:% simv -sThe following is the output whi

xxixArrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-20Dynamic Arrays . . . . . . . . . . . . . .

9-18Using the Old Command Line Interface (CLI)CPU 0 releases bus on arb0Line break at time 2050 breakpoint #3 break at memsys1.vr:69cli_6 &

9-19Using the Old Command Line Interface (CLI)} // end of program memsys_test// Don’t allow inputs to dut to floattask init_ports () { printf(“Task

9-20Using the Old Command Line Interface (CLI) printf(“\nThe memory0 address is being repeated\n\n”); printf(“\n mem_add0[%b] is

9-21Using the Old Command Line Interface (CLI) cpu1.delay_cycle(); } } join}Use the following command line to compile the design and t

9-22Using the Old Command Line Interface (CLI)Task init_portsTask reset_sequenceScope break at time 1250 breakpoint #2 break in memsys_test_top.vshel

9-23Using the Old Command Line Interface (CLI)CPU 1 readOp: address 97 data f1READ address = 097, data = 0f1 CPU 1 releases bus on

9-24Using the Old Command Line Interface (CLI)

10-1Post-Processing10Post-Processing 2• Use the $vcdpluson system task to generate VPD files. For more details on this system task, see "System T

10-2Post-Processing• Line Tracing• Delta Cycle• Verilog HDL offers the advantage of having the ability to access any internal signals from any other h

10-3Post-ProcessingSyntax:$vcdplusevent(net_or_reg,"event_name", "<E|W|I><S|T|D>"); eVCD You can use $dumpports or $ls

xxxScope Resolution Operator :: . . . . . . . . . . . . . . . . . . . . . . 24-54super keyword . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10-4Post-ProcessingVerilog HDL offers the advantage of having the ability to access any internal signals from any other hierarchical block without hav

11-1Race Detection11Race Detection 1VCS provides a dynamic race detection tool that finds race conditions during simulation and a static race detectio

11-2Race DetectionThe Dynamic Race Detection ToolThe dynamic race detection tool finds two basic types of race conditions during simulation:• read - w

11-3Race DetectionIn this example, at simulation time 5, different initial blocks assign 0 and 1 to signal a. When simulation time 5 is over you do no

11-4Race DetectionTherefore even when a Verilog design appears to be simulating correctly and you see the results you want, you should look for race c

11-5Race DetectionSpecifying the Maximum Size of Signals in Race ConditionsYou use the +race_maxvecsize compile-time option to specify the largest vec

11-6Race DetectionNote: The race.unique.out is automatically created by the PostRace.pl Perl script after simulation. This script needs a perl5 interp

11-7Race DetectionThe following is the source file, with line numbers added, for this race condition report:1. module test;2. reg a,b,c,d;3.4. alwa

11-8Race Detection• Also at simulation time 1 there is a procedural assignment to reg c on line 5 and the value of reg c is in an expression that is e

11-9Race Detection-sig signalSpecifies the signal that you want to examine for race conditions. You can only specify one signal and must not include a

xxxiControlling Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-102Disabling Random Variables . . . . . . . . . . . . . . .

11-10Race DetectionThe following is an example of the command line:PostRace.pl -minmax 80 250 -f mydesign.race.out -o mydesign.race.out.postIn this e

11-11Race DetectionWhen you have two VCD files, find their differences with the vcdiff utility. This utility is located in the vcs_install_dir/bin dir

11-12Race DetectionMethod 2: If the Number of Unique Races is LargeIf there are many lines in the race.unique.out file then there are a large number o

11-13Race Detectionb. Look for a race condition on that signal at that time. Enter:PostRace.pl -sig signal -minmax time time2If there is a race condit

11-14Race Detection 35 always @( A or C ) begin 36 D = C; 37 B = A; 38 end 39 40 assign C = B;The race.out.static file from

12-1Delays and Timing12Delays and Timing 1This chapter covers the following topics:• Transport and Inertial Delays• Pulse Control• Specifying the Dela

12-2Delays and TimingTransport and Inertial DelaysDelays can be categorized into transport and inertial delays. Transport delays allow all pulses that

12-3Delays and TimingYou can apply transport delays on all module path delays and all SDF INTERCONNECT delays backannotated to a net from an SDF file.

12-4Delays and TimingDifferent Inertial Delay ImplementationsFor compatibility with the earlier generation of Verilog simulators, inertial delays have

12-5Delays and TimingFigure 12-3 Gate Terminal WaveformsIn the example illustrated in Figure 12-3, the following occurs:1. At time 3 the input termina

xxxiisort(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-166rsort() . . . . . . . . . . . . . . . . . . . . . .

12-6Delays and Timing6. At time 14 the output is already 1 so there is no value change. The narrow pulse on the input between time 9 and 12 is filtere

12-7Delays and TimingEnabling Transport DelaysTransport delays are never the default delay. You can specify transport delays on module path delays wit

12-8Delays and Timing• Have VCS replace even narrower pulses with an X value pulse on the output and display a warning message.• Have VCS then filter

12-9Delays and TimingYou can use pulse control with transport delays (see "Pulse Control with Transport Delays" on page 12-9) or inertial de

12-10Delays and TimingYou specify transport delays for INTERCONNECT delays on nets with the +transport_int_delays, +pulse_int_e/number, and +pulse_int

12-11Delays and Timing2. At time 29 the input port toggles to 0 ending a nine time unit wide value 1 pulse on the input port.3. At time 30 the output

12-12Delays and TimingPulse Control with Inertial DelaysYou can enter the +pulse_e/number and +pulse_r/number or +pulse_int_e/number and +pulse_int_r/

12-13Delays and TimingFigure 12-5 shows the waveforms for the input and output ports for an instance of a module that models a buffer with a ten time

12-14Delays and Timing3. At time 26 the input port toggles to 0. This cancels the current scheduled second event and replaces it by scheduling a trans

12-15Delays and TimingIn the example illustrated in Figure 12-6 the following occurs:1. At simulation time 20 the input port transitions to 0. This sc

xxxiiiReclaiming Named Events . . . . . . . . . . . . . . . . . . . . . . . . 24-186Event Comparison . . . . . . . . . . . . . . . . . . . . . . . . .

12-16Delays and Timingmodule_instance_name, Value = StE port_name ---> port_name = 10;8. At time 60 the output transitions to 0.Pulse control somet

12-17Delays and TimingHere you include the +pulse_e/100 and +pulse_r/0 options. The scheduling problem is that the leading edge of the pulse on the in

12-18Delays and TimingFigure 12-8 Using +pulse_on_eventIn most cases where the +pulse_e/number and +pulse_r/number options already create X value puls

12-19Delays and TimingIn this example, by including the +pulse_on_detect option, VCS causes the leading edge of the X value pulse on the output to beg

12-20Delays and Timing4. At time 16 the input toggles to 0 scheduling a second event on the output at time 20, a transition to 0. This event also is t

12-21Delays and TimingExample 12-11 Conflicting Delay Modes‘timescale 1 ns / 1 nsmodule design (out,in);output out;input in;wire int1,int2;assign #4 o

12-22Delays and TimingThere are other modes that you can specify:• If you include the +delay_mode_unit compile-time option, VCS ignores the module pat

13-1SDF Backannotation13SDF Backannotation 1This chapter covers the following topics:• Using SDF Files• Compiling the ASCII SDF File at Compile-Time•

13-2SDF BackannotationUsing SDF FilesThe OVI Standard Delay File (SDF) specification provides a standard ASCII file format for representing and applyi

13-3SDF BackannotationCompiling the SDF file, when you compile your Verilog source files, creates binary data files that VCS reads when it executes a

xxxivEvent Expression/Structure . . . . . . . . . . . . . . . . . . . . . . . . . . 24-213Null Comparison . . . . . . . . . . . . . . . . . . . . . .

13-4SDF BackannotationThe syntax for the $sdf_annotate system task is as follows:$sdf_annotate ("sdf_file"[, module_instance] [,"sdf_co

13-5SDF Backannotation"scale_type"Specifies the delay value from each triplet in the SDF file for use before scaling. Possible values: "

13-6SDF Backannotationinput CK, D;specify (D *> out) = (1,2); (CK *> out) = (3);endspecifyendmodulemodule leafB(out,D,CK);output out;input D;inp

13-7SDF Backannotation ) ))The following is the vcs command line that compiles both the Verilog source file and the SDF file:vcs +compsdf ex.vYo

13-8SDF BackannotationBy default the +csdf+precompile option creates the precompiled SDF file in the same directory as the ASCII text SDF file and dif

13-9SDF BackannotationFor example, in the /u/designs/mydesign directory are the design.v and design.sdf files and the sdfhome directory. If you enter

13-10SDF BackannotationReading the ASCII SDF File During RuntimeYou can use the ACC capability support that is part of the PLI interface to tell VCS t

13-11SDF BackannotationFor example, the SDF annotation of module paths contained within the hierarchy of a module named myasic requires a PLI table su

13-12SDF Backannotationendendmodulemodule leaf(in,out);input in;output out;buf(out,in);specifyspecparam mpath_d=1.0;(in => out) = (mpath_d);endspec

13-13SDF Backannotation0 0 x5 0 0$finish at simulation time 100V C S S i m u l a t i o n R e p o r tTime: 100 nsCPU Time: 0.100 seconds; Data stru

xxxvUCLI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-247CLI Interface. . . . . . . . . . . . . . . . . . . . . . .

13-14SDF BackannotationUsing the Shorter Delay in IOPATH EntriesIt is valid syntax in an SDF file to have two IOPATH entries for the same pair of port

13-15SDF BackannotationVCS does not however backannotate the module path delay values as specified. Instead VCS backannotates the shorter of the corre

13-16SDF BackannotationIf an SDF file backannotates delay values to an instance of a module that must be renamed, the CELLTYPE entry in the SDF file f

13-17SDF BackannotationDelay Objects and ConstructsThe mapping from SDF statements to simulation objects in VCS is fixed, as shown in Table 13-1.Table

13-18SDF BackannotationSDF Configuration File CommandsThis section explains the commands used in SDF configuration files, with syntax and examples. ap

13-19SDF BackannotationSyntax:INTERCONNECT_MIPD = MINIMUM | MAXIMUM | AVERAGE | LAST;Example:INTERCONNECT_MIPD=LAST;map_command:This command maps the

13-20SDF BackannotationTYPICALAnnotates the typical delay valueMAXIMUMAnnotates the maximum delay valueTOOL_CONTROLDelay value is determined by the co

13-21SDF BackannotationFROM_MAXIMUMScales from the maximum timing specification in the SDF file.FROM_MTMScales directly from the minimum, typical, and

13-22SDF BackannotationSyntax:TURNOFF_DELAY = FROM_FILE | MINIMUM | MAXIMUM | AVERAGE ;Example:TURNOFF_DELAY=FROM_FILE;modulemap_command:Redirects the

13-23SDF Backannotation| path_declaration = IGNORE ;The SDF annotator uses hierarchical_path as the Verilog hierarchical path name of a submodule with

xxxviPreventing Mangling of Top-Level Modules. . . . . . . . . . . . . . 25-24Appendix A. VCS Environment VariablesSimulation Environment Variables. .

13-24SDF Backannotationtiming_check_condition: expression list_of_path_declaration: path_declaration ';'| list_of_path_declaration path_decl

13-25SDF Backannotationidentifier: verilog_id | identifier_head verilog_ididentifier_head : verilog_id '.' | identifier_head verilog_id &apo

13-26SDF Backannotationsub Y (w1,w2,in,in,ctrl,ctrl);sub W (out1,out2,w1,w2,ctrlw,ctrlw);initial begin$display(" i c ww oo");$display(&qu

13-27SDF Backannotationinput ia,ib;output oa,ob;specify(ia *> oa) = 99.99;(ib *> ob) = 2.99;endspecifyendmoduleSDF File: test.sdf(DELAYFILE(SDFV

13-28SDF BackannotationMODULE sub {SCALE_TYPE=FROM_MTM;SCALE_FACTORS=1:2:3;MTM=MINIMUM;MAP_INNER = X;(i1 *> o1) = IGNORE;(i1 *> o1) = ADD { (ia

13-29SDF Backannotation• If DEVICE does not include an output port name, VCS assigns the value to all the pin-to-pin delay (tpd) generics in the cell.

13-30SDF BackannotationHandling Backannotation to I/O PortsSDF Reader might incorrectly handle the DEVICE construct for an output I/O port if the DEVI

13-31SDF BackannotationTo handle I/O ports, use the INTERCONNECT construct instead of the DEVICE construct.Using the INTERCONNECT ConstructThe INTERCO

13-32SDF BackannotationThe SDFPOLICY variable allows you to select the backannotation delay value. You can set this variable to MIN, MAX, or MINOMAX.

13-33SDF BackannotationFigure 13-1 Net with Multiple DriversThe SDF file could specify different delays between output port lout1 and input port right

xxxviiOptions for Profiling Your Design. . . . . . . . . . . . . . . . . . . . . . B-37Options for File Containing Source File Names and Options B-38O

13-34SDF BackannotationNote: In delay value lists in delay definition entries in an SDF file, you can list one, two, three, or six delay values. List

13-35SDF BackannotationSimultaneous Multiple Source TransitionsWhen there are simultaneous transitions on more than one source port instance, the algo

13-36SDF BackannotationFigure 13-2 illustrates the following series of events:1. At time 10 output port lout1 transitions to 1. Net int transitions th

13-37SDF BackannotationNote: In delay value lists in delay definition entries in an SDF file, you can list one, two, three, or six delay values. VCS

13-38SDF BackannotationInclude the +mindelays compile-time option to specify using the minimum delay of the min:typ:max delay value triplet either in

13-39SDF BackannotationUsing the +allmtm compile-time option tells VCS to write three different compiled SDF files when VCS compiles the ASCII text SD

13-40SDF BackannotationnoIopathSpecifies disabling the module path delays in the specified module instances.noSpecifySpecifies disabling the specify b

13-41SDF BackannotationTimopt then displays the percentage of identified sequential devices to which it can actually apply optimizations followed by m

13-42SDF BackannotationTimopt will make the additional optimizations that it did not make because it was unsure of the signals and sequential devices

13-43SDF BackannotationEditing the timopt.cfg FileWhen editing the timopt.cfg file, first edit the potential sequential device entries. Edit the poten

ii2. Modeling Your DesignAvoiding Race Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2Using and Setting a Value at the Same

xxxviiiTetraMAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-59Make Accessing an Undeclared Bit an Error Condition . .

13-44SDF Backannotation1. Remove the clock signal entries from the timopt.cfg file 2. Recompile the design with the same +timopt+clock_period compile-

14-1Negative Timing Checks14Negative Timing Checks 1Negative timing checks are either $setuphold timing checks with negative setup or hold limits, or

14-2Negative Timing Checks• How VCS Calculates Delays• Using Multiple Non-Overlapping Violation WindowsThe Need for Negative Value Timing ChecksNegati

14-3Negative Timing ChecksFigure 14-1 Positive Setup and Hold LimitsHere both the setup and hold limits have positive values. When this happens the vi

14-4Negative Timing ChecksWhen this happens, use the $setuphold timing check in the top-level module of the cell to look for timing violations when si

14-5Negative Timing ChecksFigure 14-3 Negative Setup LimitHere the $setuphold timing check is in the specify block of the top-level module of the cell

14-6Negative Timing ChecksFigure 14-4 ASIC Cell with Long Propagation Delays on Data EventsThe violation window shifts to the left when there are long

14-7Negative Timing ChecksHere the $setuphold timing check is in the specify block of the top-level module of the cell. It specifies that there is a t

14-8Negative Timing ChecksThe following additional arguments are optional:timestamp_condThis argument specifies the condition which determines whether

14-9Negative Timing Checksdelayed_data_signalThe name of the delayed version of the data signal.The following example demonstrates how to use the exte

xxxixOptions for Controlling $gr_waves System Task Operations. C-17Options for VCD Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14-10Negative Timing Checks r 1 0 ? : ? : 1 ; f ? 0 ? : ? : - ; ? ? r ? : ? : 0 ;

14-11Negative Timing ChecksThe $recrem Timing Check SyntaxThe $recrem timing check syntax is very similar to the extended syntax for $setuphold:$recre

14-12Negative Timing Checkstimestamp_condThis argument specifies the condition which determines whether or not VCS reports a timing violation.In the r

14-13Negative Timing Checksdelayed_data_signalThe name of the delayed version of the data signal, typically a clock signal.Enabling Negative Timing Ch

14-14Negative Timing ChecksSimilarly, if you include the +neg_tchk compile-time option and then include the +notimingcheck runtime option instead of t

14-15Negative Timing Checks dff dff1(q, clk, d, rst); initial begin$monitor($time,,clk,,d,,q);rst = 0; clk = 0; d = 0;#100 clk = 1;#100 clk = 0;

14-16Negative Timing Checks ? ? ? * : ? : x ;endtableendprimitiveIn this example, if you include the +neg_tchk compile-time op

14-17Negative Timing ChecksIf you include the +neg_tchk compile-time option and also the +old_ntc compile-time option, the $width timing check does no

14-18Negative Timing ChecksThe timing violation, as represented by the X value, is lost to the design. If a module path delay that is greater than ten

14-19Negative Timing Checks• If the operands in these expressions are the original reference and data signals and not the delayed versions, then you w

xlCompiler Directive for Including a Source File . . . . . . . . . D-8Compiler Directive for Setting the Time Scale . . . . . . . . . D-9Compiler Dire

14-20Negative Timing Checks• You compiled your design with the +neg_tchk compile-time option.• For all $setuphold timing checks the positive setup or

14-21Negative Timing ChecksVCS uses the limits you specify in the $setuphold or $recrem timing check to calculate the delays on the delayed versions o

14-22Negative Timing ChecksHere:• The first $setuphold timing check specifies the delay on del_CP is more than 10 but less than 20 time units more tha

14-23Negative Timing ChecksIn unusual and rare circumstances multiple $setuphold and $recrem timing checks, including those that have no negative limi

14-24Negative Timing Checks #45 in1=1; endinitial begin clk=0; #50 clk = 1; #50 clk = 0;endendmodulemodule FD1 (d, cp, q);input d, cp;output

14-25Negative Timing ChecksSo the timing checks are now:$setuphold( posedge cp, negedge d, 40, -30, notifier);$setuphold( posedge cp, posedge d, 20, -

14-26Negative Timing ChecksThe $setuphold timing checks now specify: • A violation window for a falling edge on signal d between 40 and 30 time units

14-27Negative Timing ChecksVCS alters the violation windows:- For the falling edge the window starts 40 time units before the reference event and ends

14-28Negative Timing Checks

15-1SAIF Support15SAIF Support 2The Synopsys Power Compiler enables you to perform power analysis and power optimization for your designs by entering

xliSystem Tasks for Probabilistic Distribution . . . . . . . . . . . . . . D-38System Tasks for Resetting VCS . . . . . . . . . . . . . . . . . . . .

15-2SAIF SupportUsing SAIF FilesVCS has native SAIF support so you no longer need to specify any compile-time options to use SAIF files. If you want t

15-3SAIF Support$toggle_startInstructs VCS to start monitoring switching activity.Syntax: $toggle_start();$toggle_stopInstructs VCS to stop monitoring

15-4SAIF Support$read_lib_saifAllows you to read in a SDPD library forward SAIF file. It registers the state and path dependent information on the sco

15-5SAIF SupportFor more details on these task calls, refer to the Power Compiler User Guide.Note:The $read_mpm_saif, $toggle_set, and $toggle_count t

15-6SAIF SupportTo generate an SDPD backward SAIF file using a forward SAIF file, do the following:initial begin$read_lib_saif(<inputFile>);$set

15-7SAIF Support

15-8SAIF Support

16-1SWIFT VMC Models and SmartModels16SWIFT VMC Models and SmartModels 1VMC models are secure, protected, and portable models of Verilog designs. They

16-2SWIFT VMC Models and SmartModels5. Compile the design with compile-time options for the SWIFT interface and then simulate your design.This chapter

16-3SWIFT VMC Models and SmartModelsAll PlatformsYou must set the LMC_HOME environment variable to the directory where you installed the models. For e

xliiacc_getmem_size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-22acc_getmem_word_int. . . . . . . . . . . . . . . . . . . . .

16-4SWIFT VMC Models and SmartModelsHP PlatformFor the HP platform, set the SHLIB_PATH environment variable. If you have already set this environment

16-5SWIFT VMC Models and SmartModelsThis command generates a Verilog template file named modelname.swift.v. For example, if you enter the following vc

16-6SWIFT VMC Models and SmartModelsThe modifications you can make are as follows:Reordering ports in the module headerIf, for example, the module hea

16-7SWIFT VMC Models and SmartModelsRedefining ParametersThe Verilog template file contains a number of parameters that are used for specifying model

16-8SWIFT VMC Models and SmartModelsFor more information on SmartModel attributes that are parameters in the Verilog template file, see the SmartModel

16-9SWIFT VMC Models and SmartModelsThe following are examples of these regs in the Verilog template file://Generating SmartModel Windows data reg [

16-10SWIFT VMC Models and SmartModelsThis example enables the monitoring of all window regs in the module instance for the model with the hierarchical

16-11SWIFT VMC Models and SmartModelsequivalent to the $swift_window_monitor_on system task described in "Monitoring Signals in the Model Window&

16-12SWIFT VMC Models and SmartModels$lm_load_fileLoads the memory contents of a file into an instance (the contents of this file are in a specific me

16-13SWIFT VMC Models and SmartModelsNote: VCS does not support two-dimensional windows for memory models and therefore has not implemented other LMTV

xliiiacc_lsi_dumpports_limit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-47acc_lsi_dumpports_misc . . . . . . . . . . . . . . . . . . .

16-14SWIFT VMC Models and SmartModelsThe following is an example of an initial block that passes commands through the command channel:initial begin#1

16-15SWIFT VMC Models and SmartModelsUsing the CLI to Access the Command ChannelYou can also use the CLI to access the command channel during simulati

16-16SWIFT VMC Models and SmartModelsCompiling and Simulating a ModelIf your design instantiates a SmartModel or a VMC model, you compile your design

17-1Using the PLI17Using the PLI 2PLI is the programming language interface (PLI) between C/C++ functions and VCS. It helps to link applications conta

17-2Using the PLI• Probabilistic distribution• Returning a string pointer to a parameter value• Extended VCD files• Line callbacks• Source protection•

17-3Using the PLI• Using VPI Routines• Writing Your Own main() RoutineWriting a PLI ApplicationWhen writing a PLI application, you need to do the foll

17-4Using the PLITo use the debugging features, do the following:1. Write a PLI table file, limiting the scope and operations of the ACC routines used

17-5Using the PLI• The function that VCS calls during compilation to check if the user-defined system task has the correct syntax. You can omit this c

17-6Using the PLIvcs_acc_user.hFor PLI applications whose functions call the special ACC routines implemented exclusively for VCS. You will find these

17-7Using the PLI• The PLI specifications for the user-defined system task or system function. These specifications must include the call function. Fo

xlivvcsSpSetPliProtectionFlag. . . . . . . . . . . . . . . . . . . . . . . . . . . E-80vcsSpWriteChar . . . . . . . . . . . . . . . . . . . . . . . .

17-8Using the PLIACC_capabilitiesSpecifications for ACC capabilities to be added, removed, or changed in various parts of the design hierarchy. For de

17-9Using the PLIPLI SpecificationsThe valid PLI specifications are as follows:call=functionSpecifies the name of call function. This specification is

17-10Using the PLImaxargs=numberSpecifies the maximum number or arguments.nocelldefinepliDisables the dumping of value change and simulation time data

17-11Using the PLIExample 2$value_passer size=0 args=2 call=value_passer persistentIn this line, there is an associated user-defined system task (beca

17-12Using the PLI• To specify the ACC capabilities that the debugging features of VCS can use. To do this, specify ACC capabilities alone on a line i

17-13Using the PLI+=Specifies adding the ACC capabilities that follow to the parts of the design that follow, as specified by module name, %CELL,%TASK

17-14Using the PLIcbka or callback_allTo be called when named and unnamed objects (such as primitive terminals) change value. frc or forceForces value

17-15Using the PLI+Specifies adding, removing, or changing the ACC capabilities for not only the instances of the specified modules but also the insta

17-16Using the PLIacc+= rw,tchk:top,bot acc-=tchk:topThis example adds the ACC capabilities for reading and writing to nets and registers, and for bac

17-17Using the PLISpecifying ACC Capabilities for VCS Debugging FeaturesThe format for specifying ACC capabilities for VCS debugging features is as fo

1-1Getting Started1Getting Started 1VCS® is a high-performance, high-capacity Verilog® simulator that incorporates advanced, high-level abstraction ve

17-18Using the PLIThe ACC capabilities and the interactive commands they enable are as follows:ACC Capability What it enables your PLI functions to d

17-19Using the PLIExample 1The following specification enables many interactive commands including those for displaying the values of signals in speci

17-20Using the PLIExample 2The following specifications enable most interactive commands for most of the modules in a design. They then change the ACC

17-21Using the PLIOne advantage to entering .o object files and .a libraries is that you do not have to recompile the PLI application every time you c

17-22Using the PLIThe level_number in this option specifies more and more ACC capabilities as follows:+acc+1 or +accEnables all capabilities except va

17-23Using the PLIThe entries in the configuration file override the ACC write-enabling entries in the PLI table file.The syntax of each type of state

17-24Using the PLImoduleKeyword specifying that the accWrite attribute in this statement applies to all instances of the modules in the list, specifie

17-25Using the PLIUsing Only the ACC Capabilities that You NeedThere are compile-time and runtime options that enable VCS and PLI applications to use

17-26Using the PLIYou should look at the contents of the pli_learn.tab file that VCS writes to see what ACC capabilities were actually used during sim

17-27Using the PLISigns of a Potentially Significant Performance GainYou might see one of following comments in the pli_learn.tab file://!VCS_LEARNED:

1-2Getting StartedVCS is also integrated with other third-party tools via the programming language interface (PLI). Also, the DirectC Interface enable

17-28Using the PLIWhen you recompile your design with the +applylearn compile-time option, it is important that you also re-enter all the compile-time

17-29Using the PLI• +multisource_int_delays or +transport_int_delays because interconnect delays need global ACC capabilities.If you enter the +applyl

17-30Using the PLIObject data model diagrams in the IEEE Verilog language reference manual specify that some VPI routines should be able to access dat

17-31Using the PLIAlso the cbValueChange callback is not supported for the following objects:- A memory or a memory word (index or element)- VarArray

17-32Using the PLIYou specify this file with the -use_vpiobj compile-time option. For example:vcs any.c any.v -use_vpiobj vpi_user.c +cli+3 +vpiPLI Ta

17-33Using the PLIInstead you enter the -load compile-time option to specify the registration routine. The syntax is as follows:-load shared_library:r

17-34Using the PLI• -load /usr/lib/mylib.so:my_registerThe registration routine my_register() is in lib1.so, which is in /usr/lib/mylib.so, and not in

17-35Using the PLIstatic void do_cleanup(int code){ /* do simv post-processing work */}int main(int argc, char *argv[]) { /* Startup code (i

17-36Using the PLI

18-1DirectC Interface18DirectC Interface 3DirectC is an extended interface between Verilog and C/C++. It is an alternative to the PLI that, unlike the

1-3Getting StartedWhat VCS SupportsVCS provides fully featured implementations of the following:• The Verilog language as defined in the IEEE Standard

18-2DirectC InterfaceSimilarly you can use DirectC to develop applications to run with VCS to which you can pass pointers to the location of simulatio

18-3DirectC InterfaceUsing Direct C/C++ Function CallsTo enable a direct call of a C/C++ function during simulation, do the following:1. Declare the f

18-4DirectC InterfaceThere are two access modes for C/C++ function calls. These modes don’t make much difference in your Verilog code; they only perta

18-5DirectC InterfaceUsing abstract access is “safer” because the library of accessory functions for abstract access has error messages to help you to

18-6DirectC InterfaceIf a C/C++ function returns a value to a Verilog register (the C/C++ function is in an expression that is assigned to the registe

18-7DirectC Interfaceattribute ::= purereturn_type ::= void | reg | bit | DirectC_primitive_type | small_bit_vectorsmall_bit_vector ::= bit [ (constan

18-8DirectC Interfacesmall_bit_vectorSpecifies a bit-width of a returned vector bit. A C/C++ function cannot return a four state vector reg but it can

18-9DirectC InterfaceNote:Argument direction, i.e. input, output, inout applies to all arguments that follow it until the next direction occurs; the d

18-10DirectC InterfaceExample 1extern "A" reg return_reg (input reg r1);This example declares a C/C++ function named return_reg. This functi

18-11DirectC InterfaceThe keyword input is omitted. This keyword can be omitted if the first argument specified is an input argument.Example 3extern s

iiiAvoiding Circular Dependency . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33Designing With $lsi_dumpports for Simulation and Test . . . .

1-4Getting Started• OpenVera Assertions (OVA) — provides an easy and concise way to describe sequences of events, and facilities to test for their occ

18-12DirectC InterfaceThis example declares a C/C++ function named memory_reorg. When we call this function the values in memory mem2 are passed to th

18-13DirectC InterfaceYou call a non-void (returns a value) C/C++ function in the same manner as you call a Verilog function call, that is, by enterin

18-14DirectC Interfacememory_reorg(mem1,mem2);In this example all the values in memory mem2 are passed to C/C++ function memory_reorg and when it fini

18-15DirectC InterfaceFor a four-state vector (denoted by the keyword reg) the Verilog data is stored in type vec32, which for abstract access is defi

18-16DirectC InterfaceFor long vectors the chunk for the least significant bits come first, followed by the chunks for the more significant bits.Figur

18-17DirectC InterfaceConverting StringsThere are no *true* strings in Verilog and a string literal, like "some_text," is just a notation fo

18-18DirectC InterfaceThis call causes a core dump because the function expects a pointer and gets some random bits instead.It may happen that a strin

18-19DirectC InterfaceSolution 2: Perform the conversion on the Verilog side. This requires some additional effort, as the memory space for a C string

18-20DirectC InterfaceUsing Direct AccessDirect access was implemented for C/C++ routines whose formal parameters are of the following types:Some of t

18-21DirectC Interface• An open bit-width for a reg makes it possible for you to pass a vector reg, so the corresponding formal parameter for a reg ar

1-5Getting Started• DirectC Interface — this interface allows you to directly embed user-created C/C++ functions within your Verilog design descriptio

18-22DirectC InterfaceIn direct access the return value of the function is always passed by value. The data type of the returned value is the same as

18-23DirectC InterfaceIf return_reg() is a C++ function, it must be protected from name mangling, as follows:extern "C" scalar return_reg(sc

18-24DirectC InterfaceExample 3Consider the following C/C++ function declared in the Verilog source code:extern void receive_pointer ( input pointer r

18-25DirectC InterfaceExample 5Consider the following C/C++ function declared in the Verilog source code:extern void incr (inout bit [] r7);Here the

18-26DirectC InterfaceHere the parameters in and out are pointers to type U. Pointers because their corresponding arguments are larger than 32 bits an

18-27DirectC InterfaceHere the parameters in and out are pointers to type double because their corresponding arguments are type real. Using the vc_h

18-28DirectC InterfaceYou can copy from these extern declarations to the function headers in your C code. If you do you will always use the right type

18-29DirectC InterfaceUB *vc_array2ElemRef(UB*, U, U)UB *vc_array3ElemRef(UB*, U, U, U)U vc_getSize(UB*,U)This routine is similar to the vc_mdaSize()

18-30DirectC InterfaceUsing vc_handleIn the function header, the vc_handle for a Verilog reg, bit, or memory is based on the order that you declare th

18-31DirectC InterfaceThe corresponding header for the C/C++ function is as follows:After declaring the vc_handles you can use them to pass data to an

1-6Getting StartedVCSiVCSi is offered as an alternate version of VCS. VCS and VCSi are identical except that VCS is more highly optimized, resulting i

18-32DirectC InterfaceThe access routines were named to help you to remember their function. Routine names beginning with vc_get are for retrieving da

18-33DirectC InterfaceHere we declare a routine named scalarfinder and input a scalar reg, a vector reg and two memories (one with scalar elements). T

18-34DirectC Interfaceint i1 = vc_isVector(h1), i2 = vc_isVector(h2), i3 = vc_isVector(h3), i4 = vc_isVector(h4);printf("\ni1=%d i2=%d i

18-35DirectC Interfaceint vc_is4state(vc_handle)This routine returns a 1 value if the vc_handle is to a reg or memory that simulates with four states.

18-36DirectC Interface vc_is4state(h3),vc_is4state(h4));printf("\nThe vc_handles to 2state are:"); printf("\nh5=%d h6=%d h7=%d

18-37DirectC InterfaceThe function prints the following:The vc_handles to 4state are:h1=0 h2=0 h3=0 h4=0The vc_handles to 2state are:h5=1 h6=1 h7=1 h8

18-38DirectC InterfaceThe function prints the following:The vc_handle to a 4state Vector is:h2=1 The vc_handles to 4state scalars or memories

18-39DirectC InterfaceThe function prints the following:The vc_handle to a 2state Vector is:h6=1 The vc_handles to 2state scalars or memories

18-40DirectC Interfaceint vc_arraySize(vc_handle)Returns the number of elements in a memory or multi-dimensional array. The previous example also show

18-41DirectC Interfaceint vc_toInteger(vc_handle)Returns an int value for a vc_handle to a scalar bit or a vector bit of 32 bits or less. For a vector

1-7Getting StartedObtaining a LicenseYou must have a license to run VCS. To obtain a license, contact your local Synopsys Sales Representative. Your S

18-42DirectC InterfaceThe following C/C++ function uses this routine:#include <stdio.h>#include "DirectC.h"void rout1 (vc_handle onebi

18-43DirectC Interface{vec32 b,*c;c=vc_4stVectorRef(h);b=*c;printf("\n b is %x[control] %x[data]\n\n",b.c,b.d);printf("\n b is %s \n\n&

18-44DirectC InterfaceSo if we modify the C/C++ function in the previous example, it is as follows:void vector_printer (vc_handle h){vec32 b,*c;c=vc_4

18-45DirectC Interfacedouble vc_getReal(vc_handle)Returns a real (double) value from a vc_handle. For example:void print_real(vc_handle h){ printf(&q

18-46DirectC Interface}The vc_putValue routine passes the string "10xz" to the reg r1 through the vc_handle. The Verilog code displays:r1=10

18-47DirectC Interfacevc_handle h4){vc_putValueF(h1,"10",’b’);vc_putValueF(h2,"11",’o’);vc_putValueF(h3,"10",’d’);vc_put

18-48DirectC InterfaceendendmoduleThis Verilog code passes the string "abc" to the C/C++ function passback by reference, and that function p

18-49DirectC Interface module Test; reg [`FILE_NAME_SIZE*8:1] file_name;// this file_name will be passed to the Verilog code that expects// a Verilog-

18-50DirectC Interface{int a,b,c,d;a=1;b=2;c=3;d=9999999;vc_putInteger(h1,a);vc_putInteger(h2,b);vc_putInteger(h3,c);vc_putInteger(h4,d);}vec32 *vc_4s

18-51DirectC Interface if (n != 1) { printf("Error: write failed.\n"); } /* write the vector into a file; vc_*stVectorRef

1-8Getting Started- Using multiple port@host in the $LM_LICENSE_FILE can cause previous VCS releases, which use pre FLEX-LM6.1 daemons, not to work. T

18-52DirectC InterfaceHere the Verilog code declares a 32-bit bit vector, r1, and a 33-bit bit vector, r2. The values of both are passed to the C/C++

18-53DirectC Interface else{ u2=0; printf("\nShort 2 state vector passed to up2\n");}} In this example the short bit

18-54DirectC Interfacevoid vc_get4stVector(vc_handle, vec32 *)void vc_put4stVector(vc_handle, vec32 *)Passes a four state vector by reference to a

18-55DirectC Interface}This function declares a vec32 array of three elements named holder. It uses three elements because its parameters are 68-bit r

18-56DirectC InterfaceUB *vc_MemoryRef(vc_handle)Returns a pointer of type UB that points to a memory in Verilog. For example:extern void mem_doer ( i

18-57DirectC Interface for ( i = 0; i < 8; i++){ memcpy(p2,p1,8); p2 += 8; }}The purpose of the C/C++ functio

18-58DirectC InterfaceIn an element in a Verilog memory, for each eight bits in the element there is a data byte and a control byte with an additional

18-59DirectC InterfaceHere there is a Verilog memory with four addresses, each element has 25 bits. This means that the Verilog memory needs eight byt

18-60DirectC InterfaceC/C++ function mem_elem_doer uses the vc_MemoryElemRef routine to return pointers to addresses 0 and 3 in Verilog memory1 and pa

18-61DirectC Interfacescalar vc_getMemoryScalar(vc_handle, U indx)Returns the value of a one-bit memory element. For example:extern void bitflipper (i

1-9Getting Started% set path=($VCS_HOME /bin\ $VCS_HOME/‘$VCS_HOME/bin/vcs -platform‘/bin\ $path)Make sure the path environment variable is set to a b

18-62DirectC InterfaceThe Verilog code displays the following:mem[0]=1mem[0]=0void vc_putMemoryScalar(vc_handle, U indx, scalar)Passes a value of type

18-63DirectC InterfaceHere when the C/C++ function is declared on our Verilog code it does not specify a bit-width or element range for the inout argu

18-64DirectC InterfaceElement mem2[0] has an X value because half of its binary value is x and the value is displayed with the %d format specification

18-65DirectC InterfaceSo type vec32 has two members, c and d, for control and data information. This routine always copies to the 0 element of the arr

18-66DirectC InterfaceThis C/C++ function declares an array of type vec32. We must declare an array for this type but we, as shown here, specify that

18-67DirectC Interfacevoid vc_get2stMemoryVector(vc_handle, U indx, U *)Copies the data bytes, but not the control bytes, from a Verilog memory elemen

18-68DirectC Interfacevoid vc_putMemoryValue(vc_handle, U indx, char *)This routine works like the vc_putValue routine except that is for passing valu

18-69DirectC Interfacechar *vc_MemoryString(vc_handle, U indx)This routine works like the vc_toString routine except that it is for passing values to

18-70DirectC Interface }}The Verilog and C/C++ code display the following:Verilog code says "mem [0] = 111"Verilog code says "mem [

18-71DirectC Interfacememcheck_vec(mem);endendmoduleThe C/C++ function that calls vc_MemoryStringF is as follows:#include <stdio.h>#include &quo

1-10Getting StartedYou can specify a different location with the VCS_CC environment variable or with the -cc compile time option.-vDisplays the versio

18-72DirectC Interfacevoid vc_FillWithScalar(vc_handle, scalar)This routine fills all the bits or a reg, bit, or memory with all 1, 0, x, or z values

18-73DirectC InterfaceThe following Verilog and C/C++ code shows how to use this routine to fill a reg and a memory these values:extern void filler (i

18-74DirectC InterfaceThe Verilog code displays the following:r1 is xxxxxxxxr2[0] is xxxxxxxxr2[1] is xxxxxxxxr3[0] is xxxxxxxxr3[1] is xxxxxxxxr1 is

18-75DirectC InterfaceVerilog memories mem, mem2, and mem3 are all arguments to the function named show. If that function is defined as follows:#inclu

18-76DirectC Interface int sum = 0; int i1, i2, i3, i4, indx; i1 = vc_getInteger(vh_indx1); i2 = vc_getInteger(vh_indx2); /* loop over all possib

18-77DirectC Interface• If the U type parameter has a value greater than 0, it returns the number of values in the index specified by the parameter. T

18-78DirectC Interfaceint vc_arraySize(vc_handle)Returns the number of elements in a memory.scalar vc_getScalar(vc_handle)Returns the value of a scala

18-79DirectC Interfacevoid vc_StringToVector(char *, vc_handle)Converts a C string (a pointer to a sequence of ASCII characters terminated with a null

18-80DirectC Interfacescalar vc_getMemoryScalar(vc_handle, U indx)Returns the value of a one bit memory element.void vc_putMemoryScalar(vc_handle, U

18-81DirectC InterfaceEnabling C/C++ FunctionsThe +vc compile-time option is required for enabling the direct call of C/C++ functions in your Verilog

1-11Getting StartedNote:For information on coverage features, see the VCS /VCS MX Coverage Metrics User Guide.Figure 1-1 illustrates the VCS workflow.

18-82DirectC InterfaceThere are suffixes that you can append to the +vc option to enable additional features. You can append all of them to the +vc op

18-83DirectC Interface function return_pointer function return_reg_____________________ [DirectC interface] _________Mixing Direct And Abstr

18-84DirectC Interface• Include the -CC option as follows:-CC "-I$VCS_HOME/include"Useful Compile-Time OptionsVCS has other compile-time opt

18-85DirectC InterfaceEnvironment VariablesThe following environment variables can be useful with DirectC. Bear in mind that command line options over

18-86DirectC Interfaceextern_func_type ::= void | reg | bit | DirectC_primitive_type | bit_vector_type bit_vector_type ::= bit [ constant_expression :

18-87DirectC Interface

18-88DirectC Interface

19-1Using the VCS / SystemC Cosimulation Interface19Using the VCS / SystemC Cosimulation Interface 1The VCS / SystemC Cosimulation Interface enables V

19-2Using the VCS / SystemC Cosimulation InterfaceWith the interface you can use the most appropriate modeling language for each part of the system, a

19-3Using the VCS / SystemC Cosimulation InterfaceNotes:• There are examples of Verilog instantiated in SystemC and SystemC instantiated in Verilog in

1-12Getting StartedFigure 1-1 Basic VCS Compilation and Simulation FlowSimulation simvDebugVCSSimulateStep1: Compilation% vcs mem.v cpu.vVerilogCode(m

19-4Using the VCS / SystemC Cosimulation Interface• Using a Customized SystemC InstallationUsage Scenario OverviewThe usage models for the VCS /System

19-5Using the VCS / SystemC Cosimulation InterfaceNote:There are examples of Verilog instantiated in SystemC, and SystemC instantiated in Verilog, in

19-6Using the VCS / SystemC Cosimulation InterfaceVerilog Design Containing SystemC Leaf ModulesTo cosimulate a Verilog design that contains SystemC a

19-7Using the VCS / SystemC Cosimulation InterfaceInput Files RequiredTo run a cosimulation with a Verilog design containing SystemC instances, you ne

19-8Using the VCS / SystemC Cosimulation InterfaceGenerating the Wrapper for SystemC ModulesYou use the syscan utility to generate the wrapper and int

19-9Using the VCS / SystemC Cosimulation Interface-cpp path_to_the_compilerSpecifies the location of the C compiler. If you omit -cpp path_to_the_comp

19-10Using the VCS / SystemC Cosimulation Interface-o nameThe syscan utility uses the specified name instead of the module name as the name of the mod

19-11Using the VCS / SystemC Cosimulation InterfaceInstantiating the Wrapper and Coding StyleYou instantiate the SystemC wrapper just like a Verilog m

19-12Using the VCS / SystemC Cosimulation Interface initial begin counter = 0; end always @(output_data_ready) begin counter = counter +

19-13Using the VCS / SystemC Cosimulation Interface ...end moduleControlling Time Scale and Resolution in a SystemC Module Contained in a Verilog Des

1-13Getting StartedCompiling the Simulation ExecutableAfter setting up your environment and preparing your source files, you are ready to compile a si

19-14Using the VCS / SystemC Cosimulation InterfaceCompiling a Verilog Design Containing SystemC ModulesTo compile your Verilog design, include the -s

19-15Using the VCS / SystemC Cosimulation Interfacevcs -cc /usr/bin/gcc -cpp /usr/bin/g++ -sysc top.v dev.vUsing GNU Compilers on LinuxOn Linux the de

19-16Using the VCS / SystemC Cosimulation InterfaceFigure 19-2 VCS DKI Communication of SystemC Design Containing Verilog ModulesInput Files RequiredT

19-17Using the VCS / SystemC Cosimulation Interface• SystemC source code including:- A SystemC top-level simulation (sc_main) that instantiates the in

19-18Using the VCS / SystemC Cosimulation InterfaceThe syntax for the vlogan command line is as follows:vlogan -sc_model modulename file.v [-cpp path_

19-19Using the VCS / SystemC Cosimulation Interface-Mdir=directory_pathWorks the same way that the -Mdir VCS compile-time option works. If you are usi

19-20Using the VCS / SystemC Cosimulation InterfaceThe module name is adder. You instantiate it in your SystemC code in main.cpp as follows:#include &

19-21Using the VCS / SystemC Cosimulation InterfaceIn this example, dev.v might contain Verilog code utilized by the adder.v module above.When you com

19-22Using the VCS / SystemC Cosimulation Interfaceextern "C" bool hdl_elaboration_only()Both will be set/yield true only during this extra

19-23Using the VCS / SystemC Cosimulation InterfaceExampleAassume that you want to instatiate the following SystemVerilog module inside a SystemC modu

ivPerformance Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23Using Local Disks . . . . . . . . . . . . . . . . . . . . . .

1-14Getting StartedBasic Compile-Time OptionsThis section outlines some of the basic compile-time options you can use to control how VCS compiles your

19-24Using the VCS / SystemC Cosimulation Interface fprintf(stderr,"Error: stub for my_export_DPI is used\n");exit(1); } ..

19-25Using the VCS / SystemC Cosimulation InterfaceUsing GNU Compilers on SUN SolarisOn Solaris the default compiler is Sun Forte CC. You can specify

19-26Using the VCS / SystemC Cosimulation InterfaceUsing a Port Mapping FileYou can provide an optional port mapping file for the syscan command with

19-27Using the VCS / SystemC Cosimulation InterfaceThe following example shows a port mapping file.Example 19-1 Port Mapping File# Port name Bits Veri

19-28Using the VCS / SystemC Cosimulation InterfaceThe data type mapping file is named cosim_defaults.map. The interface looks for and reads the data

19-29Using the VCS / SystemC Cosimulation InterfaceVerilog * bit_vector ucharVerilog * bit_vector shortVerilog * bit_vector ushor

19-30Using the VCS / SystemC Cosimulation Interfacevcs -sysc -R -o simv top.vIf you instantiate Verilog code in SystemC:syscsim -R -o simv dev.vDebugg

19-31Using the VCS / SystemC Cosimulation Interface% ps -e | grep simv12216 pts/1 0:00 simv5. You then can launch your debugger as outlined above

19-32Using the VCS / SystemC Cosimulation Interfacethe other part at the hardware level and have full control over the level of detail required for yo

19-33Using the VCS / SystemC Cosimulation InterfaceInterface Definition FileThe interface definition file contains all the necessary information to ge

1-15Getting Started+define+macro=value+Defines a text macro in your source code to a value or character string. You can test for this definition in yo

19-34Using the VCS / SystemC Cosimulation InterfaceThe direction field specifies the caller and callee language domains, and defaults to sv_calls_sc.

19-35Using the VCS / SystemC Cosimulation InterfaceThe return keyword is only allowed once for each task. It becomes an output argument on the Verilo

19-36Using the VCS / SystemC Cosimulation InterfaceGeneration of the TLI AdaptersThe following command generates SystemVerilog and SystemC source code

19-37Using the VCS / SystemC Cosimulation InterfaceTransaction Debug OutputSince the transaction information traveling back and forth between SystemVe

19-38Using the VCS / SystemC Cosimulation InterfaceNote: Do not manually modify the code generated by the TLI adapter. Instead, override the debug fun

19-39Using the VCS / SystemC Cosimulation Interfaceformat of debug information that the adapter prints when an interface method is called. If the LSB

19-40Using the VCS / SystemC Cosimulation InterfaceThe Verilog adapter is a group of task definitions and other statements that must be included in a

19-41Using the VCS / SystemC Cosimulation InterfaceFor the integral data types in the above table, the signed and unsigned qualifiers are allowed and

19-42Using the VCS / SystemC Cosimulation InterfaceMiscellaneousThe TLI generator uses Perl5 which needs to be installed on the local host machine. Pe

19-43Using the VCS / SystemC Cosimulation InterfaceUsing a Customized SystemC InstallationYou can install the OSCI SystemC simulator and instruct VCS

1-16Getting Started+notimingcheckSuppresses timing check system tasks during compilation. This option can moderately improve simulation performance. T

19-44Using the VCS / SystemC Cosimulation Interface• Set the SYSTEMC_OVERRIDE environment variable to the user defined OSCI SystemC library installati

19-45Using the VCS / SystemC Cosimulation InterfaceIf you use the option -sysc=<version>, you must use it consistently during both analysis and

19-46Using the VCS / SystemC Cosimulation Interface

20-1Using OpenVera Assertions20Using OpenVera Assertions 1This chapter introduces the OpenVera Assertions (OVA) language and explains how to compile a

20-2Using OpenVera Assertions• Using Verilog Parameters in OVA Bind Statements• OVA System Tasks and FunctionsFor a detailed decsription of OpenVera A

20-3Using OpenVera AssertionsOVA performs the following tasks:• Tests Verilog, VHDL, and mixed-HDL designs using VCS and VCS MX.• Automatically tests

20-4Using OpenVera AssertionsHow Sequences Are Tested Using the assert DirectiveTesting starts with a temporal assertion file, which contains the desc

20-5Using OpenVera AssertionsExample 20-1 Temporal Assertion File, cnt.ova/* Define a unit with expressions and assertions (or select one from the Che

20-6Using OpenVera AssertionsFigure 20-1 Assertion Attempts for cnt.ovaImportant:Synopsys recommends always specifying a clock signal for an assertion

20-7Using OpenVera AssertionsYou can also increment a second counter using the compile-time option ova_enable_dialog. In this case, the first counter

1-17Getting Started-sverilogEnables the use of SystemVerilog code.+v2kEnables language features in the IEEE 1364-2001 standard. -v filenameSpecifies a

20-8Using OpenVera AssertionsChecking OVA Code With the Linter OptionThe linter option adds predefined rules. Rule violations other than syntax / sema

20-9Using OpenVera AssertionsIf used without any Verilog design file, only the OVA files are analyzed (including bind statements), and potential probl

20-10Using OpenVera AssertionsWhenever "a" is false, event "e1" will match because the "if - then" implication is satisf

20-11Using OpenVera AssertionsConsider rephrasing the expression using for instance a disjunction, e.g., if m is 0 then (a*[1..n] #k b) || (#(k-1) b)

20-12Using OpenVera Assertions posedge a ? 10'd1 : cnt > 10'd1000 ? cnt :

20-13Using OpenVera AssertionsGR17: RECOMMENDATION for loop over events / assertions with large (>20) ranges with loop index appearing in delay or

20-14Using OpenVera AssertionsGR27: WARNING assert check over a non-bool sequence that does not start with an "if".Example:event e: a #1 b;a

20-15Using OpenVera AssertionsGR32: WARNING the unit instance name in a bind statement is missing.The problem is that an automatically generated name

20-16Using OpenVera AssertionsThe problem is that any evaluation attempt that matches on "a" will remain active till the end of simulation,

20-17Using OpenVera AssertionsThis type of an assertion cannot be used effectively as an assumption in Magellan because it requires constraining the s

1-18Getting StartedOn Solaris, HP, and Linux machines, VCS can generate object files from your Verilog source files and does so by default. This is so

20-18Using OpenVera AssertionsTry to rewrite event "e2" without the use of "matched". In the case of our simple example, the solut

20-19Using OpenVera AssertionsCompiling Temporal Assertions FilesTemporal assertions files are compiled concurrently with Verilog source files. You ca

20-20Using OpenVera Assertions-ova_dir pathnameSpecifies an alternative name and location for the Verification Database directory. There is no need to

20-21Using OpenVera AssertionsFor example it can be:top.\gen_2.aova2 .cover_temp_no_vacuous_f_eq_t, 4 total match, 4 first match-ova_inlineEnables com

20-22Using OpenVera Assertions-ova_report [filename]Generates a report file in addition to printing results on your screen. Specifying the full path n

20-23Using OpenVera Assertions-ova_simend_max_fail NTerminates the simulation if the number of failures for any assertion reaches N. N must be supplie

20-24Using OpenVera AssertionsFunctional Code Coverage OptionsFunctional coverage is code coverage for your OVA code. With functional coverage enabled

20-25Using OpenVera Assertions• Post-process a compiled design several times with different temporal assertions files each time. You can observe the e

20-26Using OpenVera AssertionsBuilding and Running a Post-ProcessorThe procedure to build and run a post-processor is as follows:1. Include either of

20-27Using OpenVera Assertions-ova_PPTells VCS to record in the verification database directory design information that is used by the post-processor.

1-19Getting Started% simv -l log +notimingcheckBasic Runtime OptionsThis section outlines some of the basic runtime options you can use to control how

20-28Using OpenVera AssertionsDuring simulation VCS writes the VPD file.4. The next step is to build the post-processor from the post-processing data

20-29Using OpenVera Assertions-vdb_lib directory_pathSpecifies an alternative location for the VDB that VCS searches for data generated during a prior

20-30Using OpenVera Assertions-vcd filename.vcdSpecifies the VCD file. The post-processor will call the vcd2vpd utility to translate it to a VPD file

20-31Using OpenVera Assertions-o simv_nameSpecifies the executable name so the post-processor knows the name and location of the post-processing engin

20-32Using OpenVera AssertionsEnables the tracing of the specified assertion in the specified instance, at the specified simulation time. ova_trace_on

20-33Using OpenVera AssertionsIn this section, reference will be made to the following four-step post-process flow:1. Capture waveforms from a simulat

20-34Using OpenVera AssertionsNote:In this discussion, the vdb directory derived from the basename given with the -o option will be referred to as sim

20-35Using OpenVera AssertionsAs you can see, in step1, we pass simv1 as the basename for the intermediate output files. In step 2, we pass the vdb di

20-36Using OpenVera AssertionsThis dump file must contain, as a minimum, any signal referenced by the OVA checkers to be post-processed. The signals u

20-37Using OpenVera AssertionsNote that OVAPP internally requires a VPD file. Therefore, if you pass a VCD file to OVAPP, it calls the vcd2vpd convert

1-20Getting Started+notimingcheckDisables timing check system tasks in your design. Using this option at runtime can improve the simulation performanc

20-38Using OpenVera AssertionsIncremental CompileThe step 2 OVA engine compile (-ova_RPP) uses incremental compile in order to speed up the compilatio

20-39Using OpenVera AssertionsReportingBy default, the assertion report generated by the OVA engine is written into ./simv.vdb/report/ova.report. In t

20-40Using OpenVera AssertionsThings to watch out for• If you pass path/name (a full path) to -ova_cov_report, fcovReport does not automatically creat

20-41Using OpenVera AssertionsViewing Output ResultsThe two main ways of viewing the results of a simulation involving OVA are:• Viewing Results in a

20-42Using OpenVera AssertionsAssertion attempts generate messages with the following format:Viewing Results with Functional CoverageAfter running a s

20-43Using OpenVera Assertions• Had successes• Had failuresCoverage is broken down by module and instance, showing the number of attempts, failures, a

20-44Using OpenVera AssertionsAssertion and Event Summary ReportSince no changes are introduced to the data collection process when generating functio

20-45Using OpenVera Assertions• The category.html file is generated when -ova_cov_category and/or -ova_cov_severity are used to filter results. Tables

20-46Using OpenVera Assertions-ova_cov_coverSpecifies reporting of cover directive information only.-ova_cov_db pathSpecifies the path of the template

20-47Using OpenVera Assertions-ova_cov_merge filenameSpecifies the path name of a functional coverage result file or directory to be included in the r

1-21Getting Started• Using the PDF files in the NanoSim installation To access the Discovery AMS documentation in Synopsys Documentation on the Web: 1

20-48Using OpenVera AssertionsUsing OVA with Third Party SimulatorsSynopsys has developed OVAsim, a PLI application that enables you to run non-Synops

20-49Using OpenVera AssertionsInlined OVA is enabled in VCS by the -ova_inline command line switch.Specifying Pragmas in VerilogInlined OVA is specifi

20-50Using OpenVera AssertionsMethods for Inlining OVAThere are four basic methods you can use to inline OVA within Verilog:• Unit Instantiation Using

20-51Using OpenVera AssertionsFigure 20-2 Methods for Inlining OVA within VerilogOVA Checker LibraryMethod #1 — Unit-based InstantiationMethod #2 — Co

20-52Using OpenVera AssertionsUnit Instantiation Using the Unit-Based Checker LibraryThe easiest and most efficient method to inline OVA is to instant

20-53Using OpenVera AssertionsNote: In all syntax styles, you can also split a pragma statement into separate lines as follows://ova bind//ova unit_na

20-54Using OpenVera AssertionsInstantiating Context-Independent Full Custom OVAYou can inline OVA within Verilog by instantiating independent custom O

20-55Using OpenVera AssertionsIn the previous example, the bind statement (// ova bind my_mutex(clk,{a,b});) calls independent OVA code located outsid

20-56Using OpenVera AssertionsTemplate Instantiation Using the Template-Based Checker LibraryYou can instantiate any template-based checker from the C

20-57Using OpenVera Assertions• You cannot mix a template instantiation and unit instantiation within the same OVA pragma using the multi-line C++ and

1-22Getting StartedMaking a Verilog Model Protected and Portable After you have successfully verified your design using VCS, you can use the Verilog M

20-58Using OpenVera AssertionsInlining Context-Dependent Full Custom OVAYou can directly inline any custom OVA code, except for the unit definition, w

20-59Using OpenVera AssertionsCase CheckingYou can perform two types of case checking when using inlined OVA:• Parallel — The actual case selection v

20-60Using OpenVera AssertionsIf the off argument is specified, full case checking is disabled unless overridden by another command or a pragma associ

20-61Using OpenVera AssertionsThe parallel_case and full_case statements enable their own type of case check on the associated case statement and disa

20-62Using OpenVera AssertionsGeneral Inlined OVA Coding GuidelinesNote the following guidelines when coding inlined OVA:• Since OVA pragmas are decla

20-63Using OpenVera AssertionsUsing Verilog Parameters in OVA Bind Statements This section describes the enhancement to VCS that allows Verilog parame

20-64Using OpenVera AssertionsThe enhancement described in this document will cause the Verilog parameters to be expanded at the time the inlined OVA

20-65Using OpenVera AssertionsFor example, the following binds would not be legal if count and delay were used by the bound unit in temporal context:

20-66Using OpenVera AssertionsRecommended MethodologyTo make use of Verilog parameters in temporal context, the binds that use such parameters must fo

20-67Using OpenVera Assertions• The -ova_exp_param option is not enabled.• Any modules to which units using Verilog parameters are bound occur only on

2-1Modeling Your Design2Modeling Your Design 1Verilog coding style is the most important factor that affects the simulation performance of a design. H

20-68Using OpenVera AssertionsThe first step generates a skeleton Verilog file containing the hierarchy of the design and the nets converted to regist

20-69Using OpenVera AssertionsSetting and Retrieving Category and Severity Attributes You can use the following system tasks to set the category and s

20-70Using OpenVera AssertionsStarting and Stopping the Monitoring of Assertions There are several methods you can use to start and stop the monitorin

20-71Using OpenVera AssertionsWithin OVA and Verilog code, arguments can be specified for one or more module names as quoted text strings (e.g.,"

20-72Using OpenVera AssertionsArguments can be specified for one or more modules, entities, and instance scopes as in the case of $ova_start. The effe

20-73Using OpenVera Assertions$ova_start(1, "mod1") // Start assertions in all // instances of module mod1 at that level only. $o

20-74Using OpenVera Assertions$ova_assertion_start("fullHierName") Starts the monitoring of the specified assetion (string). Controlling the

20-75Using OpenVera Assertions- "continue" — Outputs the message associated with the assertion failure but otherwise has no effect on the si

20-76Using OpenVera AssertionsThe evaluation of the uses the sampled values of the variables as in the assertion. $ova_current_timeReturns current sim

20-77Using OpenVera AssertionsNote that you can specify all OVA system tasks and functions described in this chapter ($ova_set_severity, $ova_set_cate

vResolving ‘include Compiler Directives . . . . . . . . . . . . . . 3-48Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-2Modeling Your Design• Memory Size Limits in VCS• Using Sparse Memory Models• Obtaining Scope Information• Avoiding Circular Dependency• Designing W

20-78Using OpenVera AssertionsCalls From Within CodeThe $ova_start, $ova_stop, and $ova_severity_action system tasks are provided to control the moni

20-79Using OpenVera AssertionsScope resolution follows the Verilog Standard (IEEE Std 1364-2001) Section 12.5. That is, if a scope argument is specifi

20-80Using OpenVera AssertionsArguments can be specified for one or more modules, entities, and instance scopes as in the case of $ova_start. The effe

20-81Using OpenVera Assertions$ova_stop(3, i1.mod1) // Stop assertions in the hierarchy// started at scope i1.mod1 to a depth 3.To specify the respons

20-82Using OpenVera AssertionsDeveloping a User Action Function Instead of specifying "continue", "stop" or "finish" as

20-83Using OpenVera Assertionscategory:24 This represents the category assigned to the assertion. It is a 24-bit integer constant. Ova_String userMess

20-84Using OpenVera Assertions

21-1OpenVera Native Testbench21OpenVera Native Testbench 1OpenVera Native Testbench is a high-performance, single-kernel technology in VCS that enable

21-2OpenVera Native TestbenchNative Testbench is built around the preferred methodology of keeping the testbench and its development separate from the

21-3OpenVera Native Testbench• Testbench Functional Coverage• Temporal Assertions• Using Reference Verification Methodology with OpenVera• Testbench O

2-3Modeling Your Designendinitial begin#10 if (a) $display("may not print");endendmoduleThe solution is to delay the $display statement with

21-4OpenVera Native Testbench• Concurrency, or spawning off of concurrent child threads from a parent thread, using fork-join with the return to the p

21-5OpenVera Native Testbench• Constraint solver for use in generating constrained random stimulus• Sequence generator for generating random stimulus

21-6OpenVera Native TestbenchBasics of an OpenVera TestbenchThis section outlines the fundamental program structure used in all OpenVera programs. As

21-7OpenVera Native TestbenchYou must include the vera_defines.vrh file if you use predefined macros such as ON, OFF, HIGH, LOW.#include <vera_defi

21-8OpenVera Native Testbench• Testbench starts executionAny variable defined in a task or function has local scope. "Hello World!"The follo

21-9OpenVera Native TestbenchStatements are indicated with a semi-colon, ; . The str variable is initialized on the next line (str = "Hello Worl

21-10OpenVera Native Testbench% ntb_template -t design_module_name [ -c clock] filename.v \[-vcs vcs_compile-time_options] Here:design_module_nameThe

21-11OpenVera Native TestbenchMultiple Program Support Multiple program support enables multiple testbenches to run in parallel. This is useful when t

21-12OpenVera Native Testbench main1.vr main1_dep1.vr main1_dep2.vr ... main1_depN.vr [NTB_options ]p

21-13OpenVera Native TestbenchSpecifying All OpenVera Programs in Configuration FileYou can specify all the OpenVera program files along with dependen

2-4Modeling Your DesignFlip-Flop Race ConditionIt is very common to have race conditions near latches or flip-flops. Here is one variant in which an i

21-14OpenVera Native TestbenchThe configuration file, could be:program main1.vr -ntb_define ONEprogram main2.vr -ntb_incdir /usr/vera/includeOne Progr

21-15OpenVera Native Testbenchprogram test1.vrprogram test2.vrYou can specify, at most, one OpenVera program file, along with its dependent OpenVera f

21-16OpenVera Native Testbench• -ntb_define macro• -ntb_incdir directory• -ntb_opts no_file_by_file_pp• -ntb_opts tb_timescale=value• -ntb_opts dep_ch

21-17OpenVera Native Testbenchntb_options -ntb_incdir /usr/muddappa/include+/usr/vera/include -ntb_opts no_file_by_file_ppFile by file preprocessing i

21-18OpenVera Native Testbench• function string vera_get_name()• function string vera_get_ifc_name()• function string vera_get_clk_name()• function in

21-19OpenVera Native TestbenchSummaryThere are three major error scenarios, when specifying OpenVera files on the command line in addition to the conf

21-20OpenVera Native TestbenchIn this example configuration file, the prog1.vr, prog2.vr and prog3.vr files contain the OpenVera program construct. Th

21-21OpenVera Native Testbench .d2 (d2), .rst_ (rst_), .clk (clk), .q1 (q1), .q2 (q2) ); initial begin SystemClock =

21-22OpenVera Native Testbench @1 duv1.d = 2 ; @1 duv1.d = 3 ; @20 duv1.q == 8'h3 ; printf("end of sim duv_test1\n") ;}/

21-23OpenVera Native Testbench output [7:0] q2 ; input rst_ ; input clk ; dff u1 (.q(q1), .d(d1), .rst_(rst_), .clk(clk)) ; dff

2-5Modeling Your DesignNote that the following change does not resolve the race condition:always @(posedge clk)#1 q = d; // race!The #1 delay simply s

21-24OpenVera Native TestbenchCompiling and Running the OpenVera TestbenchThis section describes how to compile your testbench with the design and ho

21-25OpenVera Native TestbenchCompiling the Testbench Separate From the OpenVera Design This section describes how to compile your testbench separatel

21-26OpenVera Native TestbenchThe following steps demonstrate a typical flow involving separate compilation of the testbench:1. Compile the testbench

21-27OpenVera Native Testbench-ntb_spathSpecifies the directory where the testbench shell and shared object files will be generated. The default is th

21-28OpenVera Native Testbenchvcs -ntb_vl dut.v name.test_top.v tb.vshellHere:-ntb_vl Specifies the compilation of all Verilog files,

21-29OpenVera Native TestbenchExample% simv +ntb_load=test1/libtb.soLimitations• The hdl_task inst_path specification should begin with a top-level mo

21-30OpenVera Native Testbench-ntb_cmpCompiles and generates the testbench shell (file.vshell) and shared object files. Use this when compiling the .v

21-31OpenVera Native Testbench-ntb_filext extensions Specifies an OpenVera file extension. You can pass multiple file extensions at the same time usi

21-32OpenVera Native Testbench-ntb_vl Specifies the compilation of all Verilog files, including the design, the testbench shell file a

21-33OpenVera Native TestbenchIn cases where the out-of-bound index is directly specified as a constant expression as in the following example there i

2-6Modeling Your Designif (state0)// do somethingendThe modification of state may propagate to state0 before the if statement, causing unexpected beha

21-34OpenVera Native Testbenchprint_deps The -print_deps option is supplied with dep_check telling the VCS compiler to output the dependencies for the

21-35OpenVera Native TestbenchExample:vcs -ntb -ntb_opts use_sigprop test_io.v \ test_io.test_top.v test_io.vrThe functions supported are:function int

21-36OpenVera Native TestbenchWithout this option, the default behavior is:1. The Vera shell module name is based on the name of the OpenVera program.

21-37OpenVera Native TestbenchRuntime Options -cg_coverage_controlThe coverage_control() system task (see the OpenVera LRM: Native Testbench for descr

21-38OpenVera Native Testbench+ntb_debug_on_error Stops the simulation when it encounters a simulation error. Simulation errors involve either an exp

21-39OpenVera Native TestbenchFor example:x == 0;x == 5;Allowed values are 0, 1, and 2. The default value is 2.If +ntb_enable_solver_trace_on_failure

21-40OpenVera Native Testbench+ntb_solver_mode=value Allows you to choose between one of two constraint solver modes. When set to 1, the solver spend

21-41OpenVera Native Testbench+vera_enable_solver_trace_on_failureEnables a mode that prints trace information only when the solver fails to compute a

21-42OpenVera Native TestbenchIf specifying a command line like the following leads to problems (error messages related to classes), adding -ntb_opts

21-43OpenVera Native TestbenchThe first command line yields the order b.vr d.vr p.vr, while the second line yields, p.vr b.vr d.vr. Circular Dependenc

2-7Modeling Your DesignTime Zero Race ConditionsThe following race condition is subtle but very common:always @(posedge clock)$display("May or ma

21-44OpenVera Native Testbench.vrp, .vrhp, or as specified using option –ntb_vipext, and others. Only the latter unencrypted files are subject to depe

21-45OpenVera Native Testbenchfiles if the latter are marked as encrypted-mode by naming them with extensions .vrp, .vrhp, or additional extensions sp

21-46OpenVera Native TestbenchEach time a user-specified activity occurs, a counter associated with the bin is incremented. By establishing a bin for

21-47OpenVera Native Testbench• Optionally, a set of state and/or transition bins that define a named equivalence class for a set of values or transit

21-48OpenVera Native TestbenchExample 21-1 shows a standalone coverage_group definition and its instantiation.Example 21-1 Defining and Instantiating

21-49OpenVera Native TestbenchMeasuring Coverage VCS computes a coverage number (or percentage) for the testbench run as a whole. Here, the coverage n

21-50OpenVera Native TestbenchBy default, VCS does not create automatic bins for ’X’ or ’Z’ values of a coverage point. For example, if a coverage poi

21-51OpenVera Native TestbenchThe following system function returns the cumulative coverage (an integer between 0 and 100) for the testbench:function

21-52OpenVera Native TestbenchThe values for -cg_coverage_control are 0 or 1. A value of 0 disables coverage collection, and a value of 1 enables cove

21-53OpenVera Native TestbenchAnother c1 = new;@(posedge CLOCK);coverage_control(0);x = 10;@(posedge CLOCK);x = 30;@(posedge CLOCK);coverage_control(1

2-8Modeling Your DesignOptimizing Testbenches for DebuggingTestbenches typically execute debugging features, for example, displaying text in certain s

21-54OpenVera Native TestbenchThe format of the text report that the URG generates is different and better than the text report that used to be genera

21-55OpenVera Native Testbench3. In order to view the results, invoke a browser (for example, invoke Mozilla):% mozilla urgReport/dashboard.html% more

21-56OpenVera Native TestbenchPersistent Storage of Coverage Data and Post-Processing Tools Unified Coverage Directory and Database ControlA coverage

21-57OpenVera Native TestbenchTable 21-1 Unique Name Generation SchemeYou can disable this method of ensuring database backup and force VCS to always

21-58OpenVera Native TestbenchLoading Coverage Data Both cumulative coverage data and instance-specific coverage data can be loaded. The loading of co

21-59OpenVera Native TestbenchIn the Example 20-4 below, there is a Vera class MyClass with an embedded coverage object covType. VCS finds the cumulat

21-60OpenVera Native TestbenchThe commands above direct VCS to find the coverage data for the specified instance name in the database, and load it int

21-61OpenVera Native Testbench-cm_name filenameAs a compile-time or runtime option, specifies an alternative test name instead of the default name. Th

21-62OpenVera Native TestbenchDepending on the nature of constraints, and the number of calls to randomize() made per class, one or the other solver m

21-63OpenVera Native Testbench5. If the switched solver succeeds, then it remains the current solver choice.6. Steps 3, 4, 5 are repeated for each cal

2-9Modeling Your DesignConditional CompilationUse ‘ifdef, ‘else, and ‘endif compiler directives in your testbench to specify which system tasks you wa

21-64OpenVera Native TestbenchNote: In this chapter the term “assertion” refers to an OVA (OpenVera Assertion) or SVA (SystemVerilog Assertion) in t

21-65OpenVera Native TestbenchNote: This is not the event as defined in Assertions but rather as used in OpenVera. Here, an event is some occurrence

21-66OpenVera Native Testbench4. Create an AssertEvent object for each event to be monitored.Including the Header FilesTo start, every file that insta

21-67OpenVera Native TestbenchExample 21-4program {...AssertEngine assert_engine = new();assert_engine.Configure(ASSERT_QUIET, ASSERT_FALSE);assert_en

21-68OpenVera Native Testbenchfile: the order might change while compiling. The GetNextAssert() function fetches more Assertion handles until it deliv

21-69OpenVera Native Testbenchvalue, call the object’s GetCount() function. In Example 21-6, the code keeps track of how many times the assertion chec

21-70OpenVera Native TestbenchOr, to watch for a global reset by the AssertEngine, use the following:AssertEvent assert_engine_reset = new(ASSERT_RES

21-71OpenVera Native TestbenchTerminating the AssertEngineWhen the testbench is completely finished with assertions, it should terminate all assertion

21-72OpenVera Native Testbench#10 dat = 0;#10 dat = 1;#10 dat = 1;#10 dat = 0;#10 dat = 0;#10 dat = 0;$finish;endinitial begin#2 syn = 0;#10 syn = 1;#

21-73OpenVera Native Testbenchprintf( "\npgm: %s Assert.GetName() = %s " , tAsrt ,Ast.GetName());Ast.EnableTrigger(Event);printf("\npgm

2-10Modeling Your DesignLater in the development cycle of the design, you can compile the design without the +define+postprocess compile-time option a

21-74OpenVera Native Testbenchevent dk2 : if (syn == 1) then #2 dsyn ;event dk3 : if (syn == 1) then #3 dsyn ;}assert ck1: check(dk1);assert ck2: chec

21-75OpenVera Native TestbenchSimulation: % simv runtime_sva_options Running OpenVera Testbench with SVA and OVA TogetherCompilation: vcs ov_options_&

21-76OpenVera Native Testbench• The automatic mapping of data types between the two languages as well as the limitations of this mapping (some data ty

21-77OpenVera Native TestbenchImporting OpenVera types into SystemVerilog OpenVera has two user defined types: enums and classes. These types can be i

21-78OpenVera Native Testbench } class Derived extends Base { virtual task vfoo(arguments) { .

21-79OpenVera Native Testbench// SystemVerilog import OpenVera::Base; class SVDerived extends Base; virtual task vmt() begin .

21-80OpenVera Native Testbenchimport OpenVera::Base;Data Type Mapping In this section, we describe how various data types in SystemVerilog are mapped

21-81OpenVera Native TestbenchMailboxes and Semaphores Mailboxes and semaphores are referenced using object handles in SystemVerilog whereas in OpenVe

21-82OpenVera Native TestbenchOnce OpenVera gets an id for a mailbox/semaphore it can save it into any integer type variable. Note that however if get

21-83OpenVera Native Testbenchfunction semaphore $get_semaphore(int id);Events The OpenVera event data type is equivalent to the SystemVerilog event d

2-11Modeling Your DesignAn example of the $test$plusargs system function is as follows:initialif ($test$plusargs("postprocess"))begin$vcdplu

21-84OpenVera Native Testbenchbase type of the enum (an integral type) and then the bit-vector conversion rules (section 2.5) are applied to convert t

21-85OpenVera Native TestbenchEnumerated types with 2-value base types will be implicitly converted to the appropriate 4-state type (of the same bit l

21-86OpenVera Native TestbenchIntegers and Bit-Vectors The mapping between SystemVerilog and OpenVera integral types are shown in the table below. Not

21-87OpenVera Native TestbenchArrays Arrays can be passed as arguments to tasks and functions from SystemVerilog to OpenVera and vice-versa. The forma

21-88OpenVera Native TestbenchSome examples of compatibility: Note:A 2-valued array type in SystemVerilog cannot be directly mapped to a 4-valued arra

21-89OpenVera Native TestbenchOpenVera: they will be implicitly converted to bit vectors of the same width. packed struct {...} s in SystemVerilog is

21-90OpenVera Native TestbenchImporting Clocking Block Members into a Modport VCS allows a reference to a clocking block member to be made by omitting

21-91OpenVera Native Testbench bit clk; . . . IFC i(clk); . . . virtual IFC.mp vmp;

21-92OpenVera Native Testbench• The modport and the virtual port have the same number of members. • Each member of the modport converted to a virtual

21-93OpenVera Native Testbench// SystemVerilog interface IFC(input clk); wire a; wire b; clocking cb @

vi5. Using the Discovery Visual EnvironmentOverview of DVE Window Configuration. . . . . . . . . . . . . . . . . . . 5-2DVE Panes . . . . . . . . . .

2-12Modeling Your DesignNo matter whether you enter the +a, +ab, or +abc plusarg, when you simulate the executable, VCS always displays the following:

21-94OpenVera Native Testbenchthe current thread is suspended until that clock edge occurs and then the value is sampled. NTB-OV implements this behav

21-95OpenVera Native Testbench• In SystemVerilog code, SystemVerilog syntax must be used to turn off/on constraint blocks or randomization of specific

21-96OpenVera Native Testbenchclass A{ B b; coverage_group cg { sample x(b.c); sample y(b.d); cross cc1(x, y); sample_event = @(

21-97OpenVera Native TestbenchVCS compile:vcs -sverilog -ntb_opts interop +Other_NTB_options -ntb_incdir incdir1+incdir2+...-ntb_define defines_for_OV

21-98OpenVera Native Testbenchand then receiving it back again, with the unsupported data items unchanged.Using Reference Verification Methodology wit

21-99OpenVera Native Testbench• RVM enhancements for assertion support in Vera 6.2.10 and later are not supported for NTB.• If there are multiple cons

21-100OpenVera Native TestbenchEnabling the NTB ProfilerThe VCS profiler has been enhanced to support NTB. The +prof option enables the profiling of O

21-101OpenVera Native Testbenchresult = a.pack(arr,index,left,right,0);}program MyTest{integer k = 0, j = 0;repeat (20){@(posedge CLOCK);fork {for (j

21-102OpenVera Native Testbenchvoid DPI_call(int a, int b){int i;for( i = 0; i < 1000; i++ ){i +=b;i *=a;do_activity( i );}}Compile:% vcs -R -ntb

21-103OpenVera Native TestbenchMyTest (1) 1.40 1 test.vr:27.

2-13Modeling Your DesignUsing the $test$plusargs system function forces VCS to consider the worst case scenario — plusargs will be used at runtime —

21-104OpenVera Native Testbench---------------------------------------------------------------------Program %Totaltime -

21-105OpenVera Native Testbench• The predefined class method, pack(), invoked at test.vr:24 consumed 0.42% of the total time.• The task MyPack()define

21-106OpenVera Native TestbenchUse ModelThe $vcsmemprof() task can be called from the CLI or the UCLI interface. The syntax for $vcsmemprof() is as fo

21-107OpenVera Native TestbenchCLI InterfaceCompile-timeThe dynamic memory profiler is enabled only if you specify +dmprof on the VCS compile-time com

21-108OpenVera Native TestbenchOnly Active Memory ReportedThe memory profiler reports only memory actively held at the current simulation time instant

21-109OpenVera Native TestbenchReports the total dynamic memory consumed in all the programs (SV/OV) and that consumed in all the modules (SV) in the

21-110OpenVera Native Testbenchinteger b;}class SecondClass {integer c;integer d[10];}task FirstTask() { FirstClass a ;a = new;delay(100);}task Second

21-111OpenVera Native TestbenchCompile:vcs -ntb +dmprof test.vr -debug_allNote: The -sverilog compile-time option is not used, since the program i

21-112OpenVera Native TestbenchVCS Memory Profiler Output========================================================== $vcsmemprof called at sim

21-113OpenVera Native Testbench_____________________________________________________________________ Dynamic Data---------

2-14Modeling Your DesignHere both the +define+comppostprocess compile-time option and the +runpostprocess runtime option are required for VCS to write

21-114OpenVera Native Testbench

22-1SystemVerilog Design Constructs22SystemVerilog Design Constructs 1This chapter begins with examples of the constructs in SystemVerilog that VCS ha

22-2SystemVerilog Design Constructs• Interfaces• Enabling SystemVerilog• Disabling unique And priority Warning MessagesSystemVerilog Data TypesSystemV

22-3SystemVerilog Design ConstructsYou can also use the signed keyword to make the bit and logic data types store signed values.Note:In SystemVerilog

22-4SystemVerilog Design Constructstypedef chandle DataBase; // Data Base implemented in C/C++import "DPI" function DataBase openDataBase(st

22-5SystemVerilog Design ConstructsUser-Defined Data TypesYou can define your own data types from other data types using the typedef construct like in

22-6SystemVerilog Design ConstructsIn this example we have declared shortint variables northsouth and eastwest, that can hold a set of unassigned cons

22-7SystemVerilog Design Constructs.lastDisplays the value of the last constant of the enumeration..nextDisplays the value of the next constant of the

22-8SystemVerilog Design ConstructsendmoduleResults from the VCS simulation are as follows:Type Colors:name value total previous next last firstred 0

22-9SystemVerilog Design Constructsmodule test;logic [31:0] log1,log2;bit [7:0] bit1;parameter type bus_t = $typeof(log1);In this type parameter, bus_

2-15Modeling Your DesignTo avoid these debugging problems, and to increase simulation performance, do the following when writing new models:1. If you

22-10SystemVerilog Design ConstructsExpression: expression"filename", line_numberStructures and UnionsYou can declare C-like structures and

22-11SystemVerilog Design Constructslogic1 = st1.lg1;longint1 = st3.st2.lg1;st1.bt1 = bit1;endYou can make assignments to an entire structure if you a

22-12SystemVerilog Design Constructsmbit1=lr[23:8];mbit2=lr[7:0]; $display("mbit1=%0b mbit2=%0b",mbit1,mbit2);endIn SystemVerilog you can en

22-13SystemVerilog Design Constructsmyreg1=u1.r2[2];endStructure ExpressionsYou can use braces and commas to specify an expression to assign values to

22-14SystemVerilog Design Constructsinitials2 = {default:0};SystemVerilog ArraysSystemVerilog has packed and unpacked arrays. In a packed array all th

22-15SystemVerilog Design ConstructsWhen assigning to a packed array you can assign any vector expression, for example:bit [1:0] b1; // packe

22-16SystemVerilog Design Constructslog2[15][1][4]=1;Here is an example in which some dimensions are packed, but another is not:logic [11:0][1:0] log3

22-17SystemVerilog Design ConstructsFigure 22-1 Packed and Unpacked Multi-dimensional ArrayThe first of the previous two assignment statements:log3[6]

22-18SystemVerilog Design ConstructsFigure 22-2 A SystemVerilog Part SelectThe second of the two previous assignment statements:log3[6][11:10]=2’b00;T

22-19SystemVerilog Design ConstructsThe testbench constructs that you can enter outside programs with this option are as follows:classes associative

2-16Modeling Your DesignVCS is optimized for simulating sequential devices. Under certain circumstances VCS infers that an always block is a sequentia

22-20SystemVerilog Design ConstructsAs you can see, in SystemVerilog, you can write to a variable using a continuous assignment, connecting it to an o

22-21SystemVerilog Design ConstructsendmoduleAutomatic VariablesYou cannot force a value on to an automatic variable. For example:task automatic my_au

22-22SystemVerilog Design ConstructsVCS displays the following warning message:Warning-[MNA] Making Task or Function Non-AutomaticMaking Task non-auto

22-23SystemVerilog Design ConstructsError-[IFRLHS] Illegal force/release left hand sideForce/Release of an unpacked array which is driven by a mixture

22-24SystemVerilog Design Constructsbeginassign l2=1;l3=1;#10 force l1=0; force l2=0; force l3=0;#10 release l1; release l2; release l3;en

22-25SystemVerilog Design ConstructsThe following are examples of these data type declarations and valid force statements to the most significant bits

22-26SystemVerilog Design ConstructsUnpacked ArraysYou can make force statements to an element of an unpacked array or a slice of elements. For exampl

22-27SystemVerilog Design ConstructsLike with force statements, you can enter a release statement for an entire array, a slice of elements in the arra

22-28SystemVerilog Design Constructstypedef struct{ int int1; bit [31:0] packedbit; integer intg1;} unpackedstruct;typedef struct packed{

22-29SystemVerilog Design Constructs• VPI force and release should behave exactly in the same manner as procedural statement force and release.• If th

2-17Modeling Your DesignAvoid Unaccelerated PrimitivesVCS cannot accelerate tranif1, tranif0, rtranif1, rtranif0, tran, and rtran switches. They are d

22-30SystemVerilog Design Constructs s_vpi_value value_s = {vpiIntVal}; value_s.value.integer = 7;... vpi_put_value(var, &value_s, NULL

22-31SystemVerilog Design Constructs=+ -= *= /= %= &= |= ^= <<= >>= <<<= >>>=The following table shows a few uses of

22-32SystemVerilog Design ConstructsStatementsThe keyword unique preceding an if or nested else if statement specifies that one, and only one, conditi

22-33SystemVerilog Design ConstructsVCS evaluates these conditional expressions in sequence to see if they are true. VCS executes the first statement

22-34SystemVerilog Design ConstructsRT Warning: More than one conditions match in 'unique case' statement. " filename.v", l

22-35SystemVerilog Design ConstructsHere VCS repeatedly does these two things: increments signal i1 and then check to see if signal r1 is at 0. If whe

22-36SystemVerilog Design Constructs if (!mode) var1 = sig1 + sig2; else var1 = sig1 - sig2; var2 = sig1 + sig2;endSystemVerilog uses the ter

22-37SystemVerilog Design Constructs var1 = sig1 + sig2; else var1 = sig1 - sig2; var2 = sig1 + sig2;endThis always block executes at time zer

22-38SystemVerilog Design ConstructsThe always_latch BlockThe always_latch block models latched behavior, combinational logic with storage. The follow

22-39SystemVerilog Design Constructs q <= d;An always_ff block can only have one event control.The final BlockThe final block is a counterpar

2-18Modeling Your DesignInferring Faster Simulating Sequential DevicesVCS is optimized to simulate sequential devices. If VCS can infer that an always

22-40SystemVerilog Design Constructs• Returning values from a task or function before executing all the statements in a task or functionTasksThe follo

22-41SystemVerilog Design Constructsinstead of input [3:2][1:0] in1• in2 takes both defaults. The default direction is an input port and the default d

22-42SystemVerilog Design Constructsfunction reg [1:0] outgo(reg [3:2][1:0] in1,in2, output int out);int funcint;funcint = in1[3] >> 1;...if (in

22-43SystemVerilog Design Constructs• in2 is a scalar port that takes both defaults, input direction and the logic data type.•out is an output port so

22-44SystemVerilog Design Constructs4. If the value of in2 is not zero, the value of the local variable funcint is returned by the function.#1 reg2=ou

22-45SystemVerilog Design ConstructsYou can specify default values for:• Input ports• Inout and ref ports (one-value arguments only; constant argument

22-46SystemVerilog Design ConstructsIn the first location, the argument overrides the default and the second default value is applied as if the functi

22-47SystemVerilog Design ConstructsYou define a SystemVerilog package between the package and endpackage keywords. You must specify an identifier for

22-48SystemVerilog Design Constructs#6 int1=7;endmoduleModules top1 and top2 share int1 in package pack1. They both declare the use of the variable wi

22-49SystemVerilog Design Constructsinitial begin #1 top_bool_value1 = top_bool_value2; #5 top_bool_value2 = FALSE;endinitial$monitor(&q

2-19Modeling Your DesignUsing either blocking or nonblocking procedural assignment statements in the always block does not prevent VCS from inferring

22-50SystemVerilog Design Constructsmodule mod1;import pack1::*;struct1 mod1struct1;struct1 mod1struct2;struct1 mod1struct3;struct1 mod1struct4;initia

22-51SystemVerilog Design ConstructsExporting time-consuming user-defined tasks is an LCA feature requiring a special license.Time-consuming user-defi

22-52SystemVerilog Design Constructs• The context keyword enables, in this case, the C or C++ language function to call the user-defined task in the S

22-53SystemVerilog Design ConstructsNotice that there is a delay in this user-defined task. This is a blocking task for the C or C++ function that cal

22-54SystemVerilog Design ConstructsThe extern declaration declares the user-defined function.The address of the int variable i is passed to the user-

22-55SystemVerilog Design Constructsparameter msb=7;typedef int myint;wire w1,w2,w3,w4;logic clk;and and1 (w2,w3,w4);tran tr1 (w1,w4);primitive prim1

22-56SystemVerilog Design Constructswire [7:0] send, receive;endinterfacemodule top1(w1);output w1;endmodulemodule top2(w1);input w1;endmoduleAll cons

22-57SystemVerilog Design Constructsmodule mod1(input int in1, byte in2, inout wire io1, io2, output mystruct out);...endmodule In the mod

22-58SystemVerilog Design ConstructsInstantiation Using Implicit .name ConnectionsIn SystemVerilog if the name and size of a port matches the name and

22-59SystemVerilog Design Constructsas asterisk to connect the signals to the ports, similar to an implicit event control expression list for an alway

2-20Modeling Your Design @ (posedge clk) q <=d;Even though clk is in an event control, it is not in the sensitivity list event control.• VCS does

22-60SystemVerilog Design ConstructsRef Ports on ModulesLike arguments to tasks that you declare with the ref keyword, you can declare module ports wi

22-61SystemVerilog Design ConstructsendmoduleIn module refportmod the port named refin1 is declared with the ref keyword. All operations done in modul

22-62SystemVerilog Design ConstructsInterfacesInterfaces were developed because most bugs occur between blocks in a design and interfaces help elimina

22-63SystemVerilog Design ConstructsAt its simplest level, an interface encapsulated communication like a struct encapsulates data:Think of a wire as

22-64SystemVerilog Design ConstructsExample 22-5 Basic InterfaceAs illustrated in this example:• In the VCS implementation, interface definitions must

22-65SystemVerilog Design Constructsand interface definitions can be in module definitions or nested in other interface definitions.• To use an interf

22-66SystemVerilog Design ConstructsUsing ModportsA modport specifies direction for a signal from a “point of view.” With these two signals in the int

22-67SystemVerilog Design ConstructsNow let’s modify the module definition for module sendmod:In the module header, in the connection list in the head

22-68SystemVerilog Design ConstructsFunctions In InterfacesIf we define a user-defined task or function in the interface, we can use the import keywor

22-69SystemVerilog Design ConstructsThis module uses the method called parity, using the syntax:interface_instance_name.method_nameEnabling SystemVeri

2-21Modeling Your DesignThe following code examples illustrate this rule:Example 1VCS infers that the following always block is combinatorial, not seq

22-70SystemVerilog Design ConstructsRT Warning: No condition matches in 'priority if' statement. " filename.v", line line_n

23-1SystemVerilog Assertion Constructs23SystemVerilog Assertion Constructs 1SystemVerilog assertions (SVA), just like OpenVera assertions (OVA), are a

23-2SystemVerilog Assertion ConstructsConcurrent assertions specify how the design behaves during a span of simulation time. Immediate AssertionsAn im

23-3SystemVerilog Assertion ConstructsIn this example the immediate assertion is labeled a1, and its expression (lg1 && lg2 && lg3) is

23-4SystemVerilog Assertion ConstructsSequence s1 specifies that signal sig1 is true and then one clock tick later signal s2 is true. In this case the

23-5SystemVerilog Assertion Constructs•At $root (in SystemVerilog $root means outside of any other definition, a sequence defined in $root is globally

23-6SystemVerilog Assertion ConstructsThe operands in the sequences need to be boolean expressions, they do not have to be just signal names. For exam

23-7SystemVerilog Assertion Constructssig1 ##1 sig2 ##1 sig2 ##1 sig2;endsequenceCan be shortened to the following:sequence s1;sig1 ##1 sig2 [*3];ends

23-8SystemVerilog Assertion ConstructsYou can specify an infinite number of repetitions with the $ token. For example:sequence s1;(sig1 ##2 sig2) [*1:

23-9SystemVerilog Assertion ConstructsThe above expression would pass the following sequence, assuming that 3 is within the min:max range.a c c c c b

vii+vpdfile to Set the Output File Name. . . . . . . . . . . . . . . . . . . 6-26+vpdfilesize to Control Maximum File Size . . . . . . . . . . . . .

2-22Modeling Your DesignModeling Faster always Blocks Whether VCS infers an always block to be a sequential device or not, there are modeling techniqu

23-10SystemVerilog Assertion Constructs$fell(expression)If the expression is just a signal, this returns 1 if the least significant bit of the signal

23-11SystemVerilog Assertion ConstructsIntersecting Sequences (And With Length Restriction)You use intersect operator to specify the match of the oper

23-12SystemVerilog Assertion ConstructsSequence s3 succeeds when either sequences s1 and s2 succeed but only when sequences s1 and s2 start at the sam

23-13SystemVerilog Assertion ConstructsSpecifying That Sequence Match Within Another SequenceYou use the within operator to require that one sequence

23-14SystemVerilog Assertion ConstructsNote:If you are referencing a sequence in another sequence, and you are using the ended method in the second se

23-15SystemVerilog Assertion ConstructsFor example:if (sequence1.triggered)Level sensitive sequence controls are documented in section 8.11, starting

23-16SystemVerilog Assertion Constructsalways @(s1)$display("sequence s1 event control at %0t\n",$time);Sequence s1 is an event control expr

23-17SystemVerilog Assertion Constructscase condition s1.triggered happeneddo while condition s1.triggeredPropertiesA property says something about th

23-18SystemVerilog Assertion ConstructsThe last property is invalid because it instantiates a sequence with a different clock tick than the clock tick

23-19SystemVerilog Assertion Constructsa1: assert property (p3(sig3,sig4));Here the property uses signals sig1 and sig2 in its sequential expression,

2-23Modeling Your DesignUsing the +v2k Compile-Time OptionThe following table lists the implemented constructs in Std 1364-2001 and whether you need t

23-20SystemVerilog Assertion ConstructsProperty p1 contains an overlapping implication. It specifies checking that (sig3 && sig4) is true and

23-21SystemVerilog Assertion ConstructsInverting a PropertyThe keyword not can also be used before the declared sequence or sequential expression, or

23-22SystemVerilog Assertion ConstructsPast Value FunctionSystemVerilog has a $past system function that returns the value of a signal from a previous

23-23SystemVerilog Assertion Constructssig1 ##1 sig2;endsequenceproperty p1;@(posedge clk) disable iff (rst) s1;endpropertya1: assert property (p1);If

23-24SystemVerilog Assertion ConstructspropertyKeyword for instantiating both a property or a sequence.p1Property instantiated in the concurrent asser

23-25SystemVerilog Assertion ConstructsLike an asserted property, VCS checks an assumed property and reports if the assumed property fails to hold.ass

23-26SystemVerilog Assertion ConstructsIn this cover statement:c1:Instance name of the cover statement. cover statements have hierarchical name beginn

23-27SystemVerilog Assertion ConstructsVCS, for example, displays the following after simulation as a result of these cover statements:"exp3.v&qu

23-28SystemVerilog Assertion Constructs- In those nine attempts there were 21 times that the sequence occurred.- There were no vacuous matches because

23-29SystemVerilog Assertion Constructsendelsebegin $display("p1 does not succeed"); failCount ++;endc1: cover property (p1)begin $display

2-24Modeling Your DesignCase Statement BehaviorThe IEEE Std 1364-2001 standards for the Verilog language state that you can enter the question mark ch

23-30SystemVerilog Assertion Constructsa1: assert property(p1) else $display("p1 Failed");endmodulebind dev dev_checker dc1 (clk,a,b);In thi

23-31SystemVerilog Assertion Constructsproperty p1; @(posedge clk) a ##1 b;endproperty a1: assert property(p1) else $display("p1 Failed");e

23-32SystemVerilog Assertion Constructsbind dev dev_check #(10) dc1 (clk,sig1,sig2);Notice that module dev_check, that contains the SVA code, also has

23-33SystemVerilog Assertion Constructs• In subsection 28.5.1 “Assertion system control,” vpiAssertionSysStart and vpiAssertionSysStop are not support

23-34SystemVerilog Assertion ConstructscbAssertionLocalVarDestroyedVCS calls this callback type when it destroys an SVA local variable. This happens w

23-35SystemVerilog Assertion ConstructsNote that if VCS duplicates the SVA local variable, the returned vpi_attempt_info structure contains the handle

23-36SystemVerilog Assertion ConstructsCompile-Time And Runtime OptionsVCS has the following compile-time option for controllong SystemVerilog asserti

23-37SystemVerilog Assertion ConstructsdumpoffDisables the dumping of SVA information in the VPD file during simulation.VCS has the following runtime

23-38SystemVerilog Assertion Constructsmaxcover=NWhen you include the -cm assert compile-time and runtime option, VCS include information about cover

23-39SystemVerilog Assertion ConstructsquietDisables the display of messages when assertions fail.quiet1Disables the display of messages when assertio

2-25Modeling Your DesignMemory Size Limits in VCSThe bit width for a word or an element in a memory in VCS must be less than 0x100000 (or 220 or 1,048

23-40SystemVerilog Assertion ConstructssuccessEnables reporting of successful matches, and successes on cover statements, in addition to failures. The

23-41SystemVerilog Assertion ConstructsSee "Compiling Temporal Assertions Files" on page 20-19, "OVA Runtime Options" on page 20-2

23-42SystemVerilog Assertion ConstructsDisabling SystemVerilog Assertions at Compile-TimeYou can specify a list of SystemVerilog assertions in your co

23-43SystemVerilog Assertion Constructs@(posedge clk) sig1 && sig2 => s2;endpropertya1: assert property (p1);a2: assert property (@(posedge

23-44SystemVerilog Assertion ConstructsOptions for SystemVerilog Assertion CoverageSystemVerilog assertion coverage monitors the design for when asser

23-45SystemVerilog Assertion Constructs-cm_assert_report path/filename Specifies the file name or the full path name of the assertion coverage report

23-46SystemVerilog Assertion ConstructsAssertion coverage can also grade the effectiveness of tests, producing a list of the minimum set of tests that

23-47SystemVerilog Assertion ConstructsThe Tcl commands provided by VCS, that you can input to fcovReport for OVA coverage reports (see "Tcl Comm

23-48SystemVerilog Assertion Constructs-cm_assert_map filenameMaps the module instances of one design onto another while merging the results. For exam

23-49SystemVerilog Assertion Constructs-cm_assert_severity int_val [,int_val...]Reports only on OpenVera assertions specified by severity value. You c

2-26Modeling Your DesignIn simulations, this memory model used 4 MB of machine memory with the /*sparse*/ pragma, 81 MB without it. There is a small r

23-50SystemVerilog Assertion Constructsfcov_get_children -instance handle array of handlesReturns an array of handles for the child instances that con

23-51SystemVerilog Assertion Constructsfcov_get_modules array of handlesReturns an array of handles for the modules that contain at least one assertio

23-52SystemVerilog Assertion Constructsfcov_get_no_of_children -bin handle int Returns total number of child bins whose parent is the bin handle handl

23-53SystemVerilog Assertion Constructsfcov_grade_instances -target value1 -metric code [-timeLimit value2]string Returns a list of the minimum set of

23-54SystemVerilog Assertion ConstructsThe names of bins in the coverage database are as follows:For SVA Assertions1attemptsHolds the count of the att

23-55SystemVerilog Assertion Constructs6vacuoussuccessHolds the count of vacuous successes.8incompletesHolds the count of unterminated attemptsFor SVA

23-56SystemVerilog Assertion Constructs2failuresHolds the count of failed attempts.3allsuccessHolds the count of succesful attempts.4realsuccessHolds

23-57SystemVerilog Assertion Constructs2. Creates the report.fcov directory in the reports directory and writes in the report.fcov directory the follo

23-58SystemVerilog Assertion ConstructsAssertions with at least 1 Real SuccessSystemVerilog and OpenVera assertions can fail at certain times during s

23-59SystemVerilog Assertion ConstructsCover Directive for Property Not CoveredThe total number and percentage of SystemVerilog assertion cover statem

2-27Modeling Your DesignObtaining Scope InformationVCS has custom format specifications (IEEE Std 1364-2001 does not define these) for displaying scop

23-60SystemVerilog Assertion ConstructsTotal number of Cover Directives for SequencesA SystemVerilog cover statement can have a sequence name for an a

23-61SystemVerilog Assertion ConstructsThis information is the total number and percentage of SystemVerilog cover statements with sequences with all m

23-62SystemVerilog Assertion ConstructsThese links are followed by general information about generating this report.The tests.html FileYou can use the

23-63SystemVerilog Assertion ConstructsNext is the same information for the category numbers you used for the SystemVerilog cover statements where the

23-64SystemVerilog Assertion ConstructsEach number is a hypertext link that takes you to a list of each type of statement, directive, or event. For as

23-65SystemVerilog Assertion ConstructsHere:0Specifies reporting on the assertion if it is active (VCS is checking for its properties) and for the res

23-66SystemVerilog Assertion ConstructsIn this example simulation, signal clk initializes to 0 and toggles every 1 ns, so the clock ticks at 1 ns, 3 n

23-67SystemVerilog Assertion ConstructsAt simulation time 5 ns VCS is tracing test.a1. An attempt at the assertion started at 5 ns. At this time VCS f

23-68SystemVerilog Assertion ConstructsAssertion System FunctionsThe assertion system functions are $onehot, $onehot0, and $isunknown. Their purposes

23-69SystemVerilog Assertion Constructs• Using attributesAfter you categorize assertions you can use these categories to stop and restart assertions.U

2-28Modeling Your Designnamed block containing the task enabling statement for this other user-defined task.If the function call is in another user-de

23-70SystemVerilog Assertion Constructs$ova_get_category("assertion_full_hier_name")or$ova_get_category(assertion_full_hier_name) System fun

23-71SystemVerilog Assertion ConstructsNote:In a generate statement the category value cannot be an expression, the attribute in the following example

23-72SystemVerilog Assertion Constructs$ova_category_stop(category) System task that stops all assertions associated with the specified category. Usin

23-73SystemVerilog Assertion ConstructsglobalDirectiveCan be either of the following values:0Enables an $ova_category_start system task, that does not

23-74SystemVerilog Assertion ConstructsglobalDirectiveCan be either of the following values:0Enables an $ova_category_stop system task, that does not

23-75SystemVerilog Assertion Constructs1. VCS looks at the least significant bit of each category and logically ands that LSB to the maskValue argumen

23-76SystemVerilog Assertion ConstructsIn this example:1. The two $ova_category_stop system tasks stop first the odd numbered assertions and then the

24-1SystemVerilog Testbench Constructs24SystemVerilog Testbench Constructs 1The new version of VCS has implemented some of the SystemVerilog testbench

24-2SystemVerilog Testbench Constructsvcs -sverilog -ntb_opts options <SV source code files>As the use of vcs indicates, SystemVerilog files are

24-3SystemVerilog Testbench ConstructsRuntime OptionsThere are runtime options that were developed for OpenVera testbenches that also work with System

2-29Modeling Your Design$display("%-i"); // displays "top.d1"endendtaskfunction my_func;input taskin;begin$display("%m

24-4SystemVerilog Testbench Constructs2Enables tracing with more verbose messages.The randomize() method is described in “Randomize Methods” on page 2

24-5SystemVerilog Testbench ConstructsThe string Data TypeThe string data type is an LCA feature.VCS has implemented the string SystemVerilog data typ

24-6SystemVerilog Testbench Constructsstring string1 = "abc";string string2 = "xyz";initialbegin$display ("string1 is \"

24-7SystemVerilog Testbench Constructstolower()Similar to the toupper method, this method returns a string with the upper case characters converted to

24-8SystemVerilog Testbench Constructssubstr()Returns a substring of the specified string. The arguments specify the numbers of the characters in the

24-9SystemVerilog Testbench ConstructsendThe $monitor system task display the following:r1 = x at 0r1 = 10 at 10r1 = 16 at 20r1 = 8 at 30r1 = 2 at 40a

24-10SystemVerilog Testbench Constructsif (string1 == "123") $display("string1 %s",string1);string1.itoa(r1);if (string1 == "

24-11SystemVerilog Testbench Constructs $display("-----Start of Program ----------------"); s.hextoa(h); $display("

24-12SystemVerilog Testbench ConstructsPredefined String MethodsSystemVerilog provides several class methods to match patterns within strings.search()

24-13SystemVerilog Testbench Constructsinteger i;string str;str = "SystemVerilog supports match( ) method";i = str.match("mat");Th

2-30Modeling Your DesignReturning Information About the ScopeThe $activeinst system function returns information about the module instance that contai

24-14SystemVerilog Testbench Constructsstring str, str1;str = "SystemVerilog supports postmatch( ) method";i = str.match("postmatch( )&

24-15SystemVerilog Testbench ConstructsThe following example illustrates the usage of the backref() function call.integer i;string str, patt, str1, st

24-16SystemVerilog Testbench ConstructsProgram blocks begin with the keyword program, followed by a name for the program, followed by an optional port

24-17SystemVerilog Testbench Constructs.prog prog1 (clk,data,ctrl); // instance of the program...endmoduleIn many ways a program definition resembles

24-18SystemVerilog Testbench ConstructsFinal BlocksThe final block is Limited Customer availability (LCA) feature in NTB (SV) and requires a separate

24-19SystemVerilog Testbench Constructstime there are other important differences in a final block. A final block is like a user-defined function call

24-20SystemVerilog Testbench ConstructsArraysDynamic ArraysDynamic arrays are unpacked arrays with a size that can be set or changed during simulation

24-21SystemVerilog Testbench ConstructsThe optional (source_array) argument specifies another array (dynamic or fixed-size) whose values VCS assigns t

24-22SystemVerilog Testbench ConstructsThe size() MethodThe size method returns the current size of a dynamic array. You can use this method with the

24-23SystemVerilog Testbench ConstructslFA1[1]=1;lFA1[0]=0;lDA1=lFA1;$display("lDA1[1] = %0d", lDA1[1]);$display("lDA1[0] = %0d",

2-31Modeling Your Design $display("%i");if ($activescope("top.d0.block","top.d1.named")) $display("%-i")

24-24SystemVerilog Testbench ConstructslDA2[0] = 0lDA2 size = 2You can assign a dynamic array to a fixed-size array, provided that they are of equival

24-25SystemVerilog Testbench ConstructsWildcard IndexesYou can enter the wildcard character as the index.data_type array_id [*];Using the wildcard cha

24-26SystemVerilog Testbench Constructsinitial begin a["sa"] = 8; a["bb"] = 15; a["ec"] = 29;

24-27SystemVerilog Testbench ConstructsfirstAssigns the value of the smallest or alphabetically first entry in the array. Returns 0 if the array is em

24-28SystemVerilog Testbench Constructs $display("the first entry is \"%s\"",s_index); do

24-29SystemVerilog Testbench ConstructsQueuesA queue is an ordered collection of variables with the same data type. The length of the queue changes du

24-30SystemVerilog Testbench ConstructsendThe $display system task displays:s1=first s2=second s3=third s4=fourthYou also assign values to the element

24-31SystemVerilog Testbench ConstructsQueue MethodsThere are the following built-in methods for queues:sizeReturns the size of a queue.program prog;i

24-32SystemVerilog Testbench ConstructsThe $display system tasks display the following:first second third forth first next somewhere second third for

24-33SystemVerilog Testbench Constructsfor (int i =0; i<strque.size; i++) $write(strque[i]," ");endThe system tasks display the follo